High K Dielectric Layer Stack for Display Devices
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Solution Overview
Problem
The formation of high K dielectric layers with non-uniform thickness profiles over surfaces with both metal and dielectric materials poses challenges in display devices, leading to issues during patterning processes.
Innovation Solution
A layer stack comprising a first dielectric layer, a metal electrode, and a high K dielectric layer deposited on a second dielectric layer, with the second dielectric layer providing a homogeneous surface for uniform deposition, and an annealing process to enhance the K value and adhesion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a high K dielectric layer is deposited directly on a surface having both metal and dielectric materials, then the capacitance increases due to higher K value, but the thickness profile becomes non-uniform due to different deposition rates on metal and dielectric portions
Solution Approach 1:
A first dielectric layer is deposited as an intermediary layer between the metal electrode and the high K dielectric layer. This intermediary layer provides a uniform deposition surface that enables the high K dielectric layer to be deposited with uniform thickness, while still achieving the desired high capacitance when the high K material is used in the capacitor structure.
Solution Approach 2:
The dielectric structure is segmented into multiple layers: a first dielectric layer for providing uniform deposition surface, and a high K dielectric layer for providing high capacitance. This segmentation allows each layer to perform its specific function optimally without compromising the other.
2Quantity of substance
If a high K dielectric layer with non-uniform thickness is formed, then the capacitance may be increased, but over-etch and under-etch occur during subsequent patterning processes
Solution Approach 1:
The first dielectric layer acts as a mediator that enables uniform deposition of the high K dielectric layer, ensuring that subsequent patterning processes experience consistent etch rates across the entire layer, thereby preventing over-etch and under-etch defects.
Solution Approach 2:
The first dielectric layer is deposited in advance to create a uniform surface topology before the high K dielectric layer deposition. This preliminary action ensures that the high K layer receives a consistent substrate surface, leading to uniform thickness and reliable patterning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures a uniform thickness profile and increased K value of the high K dielectric layer, improving capacitance and adhesion, thereby addressing the non-uniformity issues in display devices.
Implementation Method 1
depositing a first dielectric layer on a second dielectric layer and a metal electrode in the plasma enhanced atomic layer deposition chamber
Implementation Method 2
annealing the high K dielectric layer in the thermal treatment chamber
Data Source
AI summary
Embodiments of the present disclosure generally relate to a layer stack including a high K dielectric layer formed over a first dielectric layer and a metal electrode. The high K dielectric layer has a K value of 20 or higher and may be formed as a part of a capacitor, a gate insulating layer, or any suitable insulating layer in electronic devices, such as display devices. The layer stack includes a second dielectric layer disposed on the first dielectric layer and the metal layer, and the high K dielectric layer containing zirconium dioxide or hafnium dioxide disposed on the second dielectric layer. The second dielectric layer provides a homogenous surface on which the high K dielectric layer is formed. The homogeneous surface enables the high K dielectric material to be deposited uniformly thereover, resulting in a uniform thickness profile.