High-k Gate Dielectric Crystallization at Reduced Anneal Temperature
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Solution Overview
Problem
The continuous scaling down of semiconductor devices to meet demands for higher performance and lower power consumption poses challenges in process control, particularly due to high-temperature crystallization of high-k dielectric layers, which can introduce defects and alter dopant profiles, affecting device performance and reliability.
Innovation Solution
A method for forming a crystalline high-k dielectric layer at a reduced crystallization temperature by doping the first high-k dielectric layer with a first metal element to form dipoles and then depositing a second high-k dielectric layer with a different metal element that diffuses as a second dopant during annealing, reducing the crystallization temperature to 500° C. to 700° C., thereby minimizing defects and maintaining stress between channel and source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If high-temperature crystallization is used to form the high-k dielectric layer, then the dielectric constant is improved, but defects are introduced and dopant profiles are altered
Solution Approach 1:
The patent changes the crystallization temperature parameter from conventional high temperatures (>800°C) to a reduced temperature range (500-700°C). This parameter change is achieved through specific heat treatment processes that enable crystallization at lower temperatures, thereby improving dielectric constant while avoiding the harmful effects of high-temperature processing on dopant profiles and interface quality
Solution Approach 2:
The patent employs a composite gate dielectric structure consisting of multiple layers including the high-k dielectric layer, interfacial layer, and cap layer. This composite structure allows the high-k layer to be crystallized at reduced temperatures while maintaining overall device performance, as the other layers provide necessary interface quality and protection
2Stability of the object's composition
If high-temperature processing is applied, then crystallization is achieved, but thermal budget increases and manufacturing complexity increases
Solution Approach 1:
The patent reduces the thermal budget by implementing crystallization at lower temperatures (500-700°C) compared to conventional high-temperature processes. This parameter change simplifies the manufacturing process by reducing the number of high-temperature steps required and minimizing thermal interactions with other device components
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces defects at the interface, minimizes dopant profile changes, and maintains stress between channel and source/drain regions, improving gate capacitance and overall device performance while reducing the thermal budget of the manufacturing process.
Implementation Method 1
The second metal element can diffuse into the first high-k dielectric layer as a second dopant during a subsequent anneal process
Implementation Method 2
crystallization temperature of the first high-k dielectric layer and can be crystallized at a lower temperature
Data Source
AI summary
The present disclosure describes forming a crystalline high-k dielectric layer at a reduced crystallization temperature in a semiconductor device. The method includes forming a channel structure on a substrate, forming an interfacial layer on the channel structure, forming a first high-k dielectric layer on the interfacial layer, forming dipoles in the first high-k dielectric layer with a dopant, and forming a second high-k dielectric layer on the first high-k dielectric layer. The dopant includes a first metal element. The second high-k dielectric layer includes a second metal element different from the first metal element.