High-k Dielectric Crystallization With Orientation Control
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Solution Overview
Problem
As semiconductor devices continue to integrate more components into a given area through reduced minimum feature sizes, challenges arise in minimizing leakage current and controlling crystalline phase and orientation of high-k gate dielectrics, which affect device performance.
Innovation Solution
A method is employed to form a crystalline high-k dielectric layer with controlled crystalline orientations by seeding and annealing amorphous high-k dielectric layers, using nucleation enhancement treatments and doping to achieve specific crystalline phases and orientations, thereby reducing leakage current and enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If amorphous high-k dielectric layers are used to reduce leakage current, then leakage current is reduced, but crystalline phase and orientation control becomes difficult affecting device performance
Solution Approach 1:
The patent applies preliminary action by performing nucleation enhancement treatments (such as plasma treatment, ion implantation, or atomic layer deposition of nucleation catalysts) on the amorphous high-k dielectric layer before the main crystallization annealing process. This preliminary treatment creates nucleation sites that guide subsequent crystallization, enabling control over crystalline phase and orientation while maintaining the low leakage current benefits of the amorphous precursor layer
Solution Approach 2:
The patent employs parameter changes by carefully controlling annealing temperature, time, and atmosphere parameters during the crystallization process. By adjusting these parameters, the amorphous high-k dielectric layer transforms into desired crystalline phases (such as orthorhombic, tetragonal, or cubic) with specific orientations, achieving both low leakage current and precise crystalline control
2Productivity
If minimum feature sizes are reduced to increase integration density, then integration density is improved, but leakage current control and crystalline phase management become more challenging
Solution Approach 1:
The patent applies local quality by implementing spatially varying nucleation enhancement treatments and doping profiles within the high-k dielectric layer. Different regions receive different treatments to achieve local control over crystalline phase and orientation, enabling reliable leakage current control even as minimum feature sizes are reduced and integration density increases
Solution Approach 2:
The patent uses parameter changes by adjusting annealing conditions, nucleation treatment parameters, and doping concentrations to maintain reliable leakage current control across different feature sizes. These parameter adjustments enable the process to scale from larger to smaller feature sizes while preserving reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method results in a crystalline high-k dielectric layer with controlled crystalline phases and orientations, reducing leakage current and improving device performance by increasing permittivity and ferroelectric properties.
Implementation Method 1
A method is employed to form a crystalline high-k dielectric layer with controlled crystalline orientations by seeding and annealing amorphous high-k dielectric layers
Implementation Method 2
using nucleation enhancement treatments and doping to achieve specific crystalline phases and orientations
Data Source
AI summary
A method for forming a crystalline high-k dielectric layer and controlling the crystalline phase and orientation of the crystal growth of the high-k dielectric layer during an anneal process. The crystalline phase and orientation of the crystal growth of the dielectric layer may be controlled using seeding sections of the dielectric layer serving as nucleation sites and using a capping layer mask during the anneal process. The location of the nucleation sites and the arrangement of the capping layer allow the orientation and phase of the crystal growth of the dielectric layer to be controlled during the anneal process. Based on the dopants and the process controls used the phase can be modified to increase the permittivity and/or the ferroelectric property of the dielectric layer.