High-k Gate Dielectric Crystallization for Leakage and Phase Control
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, challenges arise in minimizing leakage current and achieving optimal integration density, particularly in forming high-k gate dielectrics for MOSFET and finFET devices, where existing methods struggle to maintain crystallinity and control crystal phases effectively.
Innovation Solution
The process involves forming an amorphous high-k dielectric layer with a capping layer to control crystallization, using nucleation enhancement treatments and doping to achieve desired crystal phases, and subsequent annealing techniques to form crystalline high-k dielectric layers with specific k-values and ferroelectric properties, ensuring minimal leakage current and improved integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but leakage current increases and controlling crystal phases becomes more difficult
Solution Approach 1:
The patent applies parameter changes by modifying the crystallization temperature and time parameters during the formation of high-k gate dielectric layers. By controlling these thermal parameters, the patent achieves desired crystal phases (such as tetragonal or cubic phases of HfO2) that provide low leakage current characteristics while maintaining the reduced feature size for high integration density.
Solution Approach 2:
The patent employs composite materials by forming high-k gate dielectric layers composed of multiple materials or compositions, such as HfO2 combined with other oxides or doped HfO2. These composite structures enable simultaneous achievement of low leakage current and stability at reduced feature sizes through synergistic material properties.
2Ease of manufacture
If conventional deposition methods are used for high-k gate dielectrics, then manufacturing is simpler, but crystallinity and crystal phase control are insufficient
Solution Approach 1:
The patent applies preliminary action by performing nucleation enhancement treatments before the main crystallization process. This includes forming seed layers or applying preliminary thermal treatments that prepare the amorphous high-k dielectric layer for controlled crystallization, enabling subsequent precise control of crystal phases while maintaining process simplicity.
Solution Approach 2:
The patent employs periodic action through multi-stage annealing processes with different temperature profiles and durations. The crystallization process is divided into multiple periodic thermal treatment steps, each targeting specific crystal phase transformations, thereby achieving precise crystal phase control while building upon conventional deposition methods.
3Productivity
If amorphous high-k dielectric layers are formed without capping layers, then deposition is faster, but crystallinity during annealing cannot be controlled
Solution Approach 1:
The patent applies the intermediary principle by introducing capping layers that act as mediators during the crystallization process. These capping layers control the thermal environment and oxygen supply during annealing, enabling controlled crystallization of the amorphous high-k dielectric layer while maintaining fast deposition speeds for the underlying dielectric material.
Solution Approach 2:
The patent applies preliminary action by forming the capping layer structure before the crystallization annealing process. This preliminary structural preparation ensures that when thermal treatment is applied, the crystallization proceeds in a controlled manner with desired crystal phases, while the fast deposition of the amorphous layer is preserved.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the crystallinity of high-k dielectric layers, achieving desired k-values and ferroelectric properties, thereby reducing leakage current and improving integration density in semiconductor devices.
Implementation Method 1
performing a crystallization process to crystallize the dielectric layer
Implementation Method 2
subsequent annealing techniques to form crystalline high-k dielectric layers
Implementation Method 3
exposing a seeding section of the dielectric layer through openings within the capping layer; performing a crystallization process to crystallize the dielectric layer
Implementation Method 4
using nucleation enhancement treatments and doping to achieve desired crystal phases
Data Source
AI summary
A method for forming a crystalline high-k dielectric layer and controlling the crystalline phase and orientation of the crystal growth of the high-k dielectric layer during an anneal process. The crystalline phase and orientation of the crystal growth of the dielectric layer may be controlled using seeding sections of the dielectric layer serving as nucleation sites and using a capping layer mask during the anneal process. The location of the nucleation sites and the arrangement of the capping layer allow the orientation and phase of the crystal growth of the dielectric layer to be controlled during the anneal process. Based on the dopants and the process controls used the phase can be modified to increase the permittivity and/or the ferroelectric property of the dielectric layer.