High-K Dielectric Stack for Sub-0.5 nm EOT
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in improving carrier mobility and reducing leakage current in advanced FinFET devices as feature sizes decrease, particularly due to limitations in existing high-K dielectric stack designs that struggle to achieve effective oxide thickness (EOT) below 0.5 nm and require different gate dielectric materials for PMOS and NMOS regions.
Innovation Solution
A high-K dielectric stack is formed using a multi-layered structure comprising hafnium oxide, hafnium lanthanum oxide, and lanthanum aluminum oxide, with a thin aluminum doped layer, which allows for electrostatic control and reduces leakage current, and is applicable to both PMOS and NMOS regions, enabling the use of the same gate dielectric materials across both types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If existing high-K dielectric stack designs are used, then manufacturing simplicity is maintained, but effective oxide thickness cannot be reduced below 0.5 nm and carrier mobility is limited
Solution Approach 1:
The gate dielectric is segmented into multiple functional layers: a first high-K dielectric layer (HfO2) providing baseline capacitance, a second high-K dielectric layer (HfLaO3) enhancing electrostatic control, and a third high-K dielectric layer (LaAlO3) with superior properties. This segmentation enables achieving EOT below 0.5 nm while maintaining manufacturing feasibility through sequential deposition processes.
Solution Approach 2:
The patent employs composite dielectric materials combining different high-K dielectrics with complementary properties. The HfO2-HfLaO3-LaAlO3 stack creates a composite structure where each material contributes specific characteristics, enabling sub-0.5 nm EOT and improved carrier mobility that single-material systems cannot achieve.
2Reliability
If different gate dielectric materials are used for PMOS and NMOS regions, then device performance is optimized, but manufacturing complexity and production costs increase
Solution Approach 1:
The three-layer high-K dielectric stack structure serves as a universal gate dielectric solution applicable to both PMOS and NMOS regions. The combination of HfO2, HfLaO3, and LaAlO3 in specific thicknesses provides the necessary electrostatic control and performance characteristics for both device types, eliminating the need for region-specific material selection and simplifying the manufacturing process.
Data Source
AI summary
A method of forming a gate dielectric material includes forming a high-K dielectric material in a first region over a substrate, where forming the high-K dielectric material includes forming a first dielectric layer comprising hafnium over the substrate, and forming a second dielectric layer comprising lanthanum over the first dielectric layer.