Dipole-Engineered High-k Gate Dielectrics for Threshold Voltage Tuning
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Solution Overview
Problem
Conventional methods for adjusting threshold voltages in MOS devices face challenges in achieving precise control and require additional steps like using different work-function metals and adjusting thickness, limiting the flexibility in voltage adjustment.
Innovation Solution
The implementation of dipole-engineered high-k gate dielectric layers, where dipole dopants are diffused into multiple high-k dielectric layers with different dielectric constants, allowing for selective threshold voltage adjustments through thermal diffusion, reducing Capacitance Equivalent Thickness (CET), and improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional thermal anneal with ammonia is used to adjust threshold voltage, then threshold voltage can be changed, but it is difficult to adjust to intended values and requires additional steps with different work-function metals
Solution Approach 1:
The patent changes the chemical composition parameter of the high-k dielectric layer by incorporating dipole-containing materials (such as metal nitrides, metal oxynitrides, or metal oxyhalides) to directly adjust the threshold voltage. This compositional parameter change enables precise threshold voltage control without requiring multiple different work-function metal layers, thereby reducing process complexity while achieving the intended voltage adjustment precision.
Solution Approach 2:
The patent uses composite high-k dielectric structures that combine high-k material with dipole-containing materials (forming a composite layer or interfacial layer). This composite structure provides both the high dielectric constant needed for device performance and the dipole moment needed for threshold voltage adjustment, eliminating the need for separate work-function metal adjustment steps.
2Adaptability or versatility
If multiple work-function metals with different thicknesses are used to adjust threshold voltage, then desired voltage levels can be achieved, but the manufacturing process becomes more complex
Solution Approach 1:
The patent makes the high-k dielectric layer multi-functional by incorporating dipole-containing materials that simultaneously provide dielectric function and threshold voltage adjustment function. This single layer performs both roles, replacing the need for multiple work-function metal layers with different thicknesses, thereby simplifying manufacturing while maintaining the ability to achieve desired voltage levels across different device types.
Solution Approach 2:
The patent introduces dipole-containing materials at specific locations within the gate stack (at the interface between the high-k dielectric and semiconductor, or as an interfacial layer) to locally adjust the electric field and threshold voltage. This localized approach provides versatile voltage tuning without requiring global changes through multiple metal layers, simplifying the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise adjustment of threshold voltages and enhances device performance by providing multiple levels of threshold voltage tuning, improving the flexibility and efficiency of MOS device manufacturing.
Implementation Method 1
dipole dopants are diffused into multiple high-k dielectric layers with different dielectric constants, allowing for selective threshold voltage adjustments through thermal diffusion
Implementation Method 2
the threshold voltages of the MOS devices may be adjusted by performing a thermal anneal process when conducting ammonia to treat the high-k dielectric layers
Data Source
AI summary
A method includes forming an oxide layer on a semiconductor region, and depositing a first high-k dielectric layer over the oxide layer. The first high-k dielectric layer is formed of a first high-k dielectric material. The method further includes depositing a second high-k dielectric layer over the first high-k dielectric layer, wherein the second high-k dielectric layer is formed of a second high-k dielectric material different from the first high-k dielectric material, depositing a dipole film over and contacting a layer selected from the first high-k dielectric layer and the second high-k dielectric layer, performing an annealing process to drive-in a dipole dopant in the dipole film into the layer, removing the dipole film, and forming a gate electrode over the second high-k dielectric layer.