High-K Gate Dielectric Dipole Stack for Threshold Voltage Tuning
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Solution Overview
Problem
The thinning of gate dielectric layers in semiconductor devices leads to increased leakage current due to direct tunneling between dielectric layers and the substrate, which is exacerbated by the use of high-k materials with poor thermal stability and phase changes at elevated temperatures.
Innovation Solution
A stack of gate dielectric layers comprising a first dielectric layer containing praseodymium (Pr) and oxygen (O) and a second dielectric layer containing aluminum and oxygen, with aluminum atoms diffusing into the first layer to form a dipole that controls the threshold voltage, and a high-k dielectric layer formed on the second layer to prevent work function alteration during subsequent processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate dielectric layers are thinned to increase integration density, then device performance and integration density improve, but leakage current increases due to direct tunneling
Solution Approach 1:
The patent employs a composite gate dielectric structure consisting of multiple layers including high-k dielectric materials (such as hafnium oxide, zirconium oxide) combined with conventional dielectric materials (such as silicon oxide). This composite structure enables achieving lower equivalent oxide thickness for higher integration density while the high-k layer provides sufficient barrier properties to suppress direct tunneling leakage current.
Solution Approach 2:
The patent applies different dielectric materials with different properties at different locations within the gate stack. The high-k dielectric layer is positioned where maximum capacitance is needed, while conventional dielectric layers are used where tunneling suppression is critical. This local optimization of material properties resolves the contradiction between thinning for density and preventing leakage.
2Object-generated harmful factors
If high-k dielectric materials are used to reduce equivalent oxide thickness, then leakage current is reduced, but thermal stability deteriorates due to phase changes at elevated temperatures
Solution Approach 1:
The patent combines high-k dielectric materials with conventional thermally stable dielectric materials in a multi-layer gate stack. The conventional dielectric layers (such as silicon oxide) provide thermal stability and prevent phase changes during subsequent processing, while the high-k layers maintain low leakage current. This composite approach resolves the contradiction between reducing leakage and maintaining thermal stability.
Solution Approach 2:
The conventional dielectric layers act as intermediary layers between the high-k dielectric materials and the substrate or other gate components. These intermediary layers provide thermal buffering and prevent direct exposure of the high-k materials to extreme temperatures that would cause phase changes, thereby maintaining both low leakage and thermal stability.
3Adaptability or versatility
If dipole layers are formed to control threshold voltage, then device tunability improves, but manufacturing complexity increases
Solution Approach 1:
The patent integrates dipole layer formation into the existing gate dielectric deposition process. The dipole-inducing elements are incorporated during the same atomic layer deposition or chemical vapor deposition steps used to form the gate dielectric layers, eliminating the need for separate dipole layer deposition processes. This merging approach provides threshold voltage tunability while minimizing manufacturing complexity.
Solution Approach 2:
The gate dielectric materials themselves are designed to provide dipole effects through their intrinsic properties and deposition conditions. By controlling deposition parameters such as oxygen partial pressure, temperature, and precursor ratios during dielectric layer formation, the desired dipole moments are self-generated without requiring additional processing steps, thus achieving tunability with minimal added complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides transistors with tunable threshold voltages and significantly reduces leakage current density, allowing for thinner layers with lower equivalent oxide thickness while maintaining thermal stability and dielectric constant, thus enhancing device performance.
Implementation Method 1
aluminum atoms diffusing into the first layer to form a dipole
Implementation Method 2
high-k dielectric layer formed on the second layer to prevent work function alteration
Implementation Method 3
leakage current increases due to the thinning of gate dielectric layers... increased leakage current density due to direct tunneling
Data Source
AI summary
A method of forming a semiconductor device includes forming a transistor comprising a gate stack on a semiconductor substrate by, at least, forming a first dielectric layer on the semiconductor substrate, forming a dipole layer on the dielectric layer; forming a second dielectric layer on the dipole layer, forming a conductive work function layer on the second dielectric layer, forming a gate electrode layer on the conductive work function layer. The method also includes varying a distance between dipole inducing elements in the dipole layer and a surface of the semiconductor substrate by tuning a thickness of the first dielectric layer to adjust a threshold voltage of the transistor.