High-k Gate Dielectric Dipole Diffusion for Threshold Voltage Tuning
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Solution Overview
Problem
The shrinking geometry of IC devices complicates the deposition of additional dipole layers and dielectric layers in gate trenches, reducing the process window for forming functional metal gate stacks, especially when the gate trenches are not straight, leading to issues in achieving desired threshold voltages.
Innovation Solution
A method involving the deposition of a first and second dipole layer over a gate dielectric layer, followed by selective removal and thermal diffusion into the dielectric layer to alter threshold voltages, ensuring uniform deposition of a functional metal gate stack across different device regions with varying threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional dipole layers and dielectric layers are deposited in gate trenches to provide transistors with different threshold voltages, then transistor threshold voltage control is improved, but the process window for depositing layers in the functional metal gate structure is reduced
Solution Approach 1:
The patent segments the gate structure into multiple regions (first device region, second device region, third device region) with different dipole layer configurations. The first dipole layer is selectively removed from the second device region, creating region-specific threshold voltage characteristics without affecting other areas, thus maintaining process window while achieving threshold voltage control.
Solution Approach 2:
The patent applies local quality by having different dipole layer structures in different device regions. The second device region has its first dipole layer removed while first and third regions retain it, creating locally optimized threshold voltages for different transistor types (e.g., NFET vs PFET) within the same gate structure.
2Length of moving object
If the gate trench dimensions are reduced due to shrinking geometry, then device scaling is achieved, but the process window for depositing additional layers is further reduced
Solution Approach 1:
The patent performs preliminary actions by forming the gate dielectric layer and first dipole layer across all device regions before selectively removing the first dipole layer from the second device region. This sequence allows uniform initial deposition and then creates regional differentiation, maintaining process window even with reduced gate trench dimensions.
3Manufacturing precision
If the gate trench is not straight, then manufacturing variations occur, but the process window is further reduced
Solution Approach 1:
The patent changes the parameter of dipole layer presence/absence to compensate for gate trench straightness variations. By selectively removing the first dipole layer from the second device region, the patent creates a robust solution that works even when gate trenches have manufacturing variations, maintaining adequate process window.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains a consistent process window for forming functional metal gate stacks with varying threshold voltages by eliminating the need for dipole layers in certain regions, thereby ensuring uniformity and functionality across transistors.
Implementation Method 1
The workpiece is annealed at a temperature between about 500° C. and about 900° C. so that ingredients in the first dipole layer and the second dipole layer thermally diffuse into the gate dielectric layer
Implementation Method 2
The workpiece is annealed at a temperature between about 500° C. and about 900° C.
Data Source
AI summary
Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first transistor having a first gate dielectric layer, a second transistor having a second gate dielectric layer, and a third transistor having a third gate dielectric layer. The first gate dielectric layer includes a first concentration of a dipole layer material, the second gate dielectric layer includes a second concentration of the dipole layer material, and the third gate dielectric layer includes a third concentration of the dipole layer material. The dipole layer material includes lanthanum oxide, aluminum oxide, or yittrium oxide. The first concentration is greater than the second concentration and the second concentration is greater than the third concentration.