High-k Gate Doping via Selective Etch and Blocking Stack
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Solution Overview
Problem
Current methods for forming gates in N- and P-type transistors in CMOS technology are cumbersome due to differences in workfunctions, requiring different metal layers, which complicates the fabrication process and can lead to adverse effects on device properties.
Innovation Solution
The use of selective etching of multi-layered stacks or controlled etching of single layered blocking stacks to form high-k replacement metal gate structures with a soft metal mask, allowing for differential doping of high-k gate dielectric layers to create threshold differences between N- and P-type FETs, using a multi-layered or single layered blocking stack as a buffer to prevent dopant migration and minimize oxygen diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different metal layers are used for NFET and PFET gates to account for workfunction differences, then the transistor performance is improved, but the fabrication process complexity increases
Solution Approach 1:
The gate structure is segmented into distinct components: a common high-k dielectric layer for both NFET and PFET, and separate metal gate layers for each transistor type. This segmentation allows each layer to be optimized independently - the high-k layer provides uniform dielectric performance while the separate metal layers address the workfunction differences, thereby maintaining transistor performance without requiring a completely different gate structure for each device type.
Solution Approach 2:
The high-k dielectric layer serves as a universal component for both NFET and PFET gates, performing the same dielectric function in both transistor types. This multi-functionality reduces fabrication complexity by allowing a single high-k layer deposition process to serve both device types, while only the metal gate layers need to be differentiated to account for workfunction variations.
2Reliability
If dopant films are patterned in high-k dielectrics to create threshold differences, then device performance is improved, but dopant diffusion and oxygen migration degrade device properties
Solution Approach 1:
A blocking stack is formed over the high-k dielectric layer before dopant deposition. This preliminary action creates a protective barrier that prevents dopant diffusion into regions where it is not desired and blocks oxygen migration during subsequent processing steps. The blocking stack is strategically positioned to establish diffusion barriers in advance, ensuring precise dopant placement and maintaining high-k dielectric integrity throughout the fabrication process.
Solution Approach 2:
The blocking stack acts as an intermediary layer between the dopant source and the high-k dielectric. This intermediate structure mediates the interaction by selectively allowing or preventing dopant and oxygen access to the high-k layer, thereby controlling diffusion processes and protecting device properties while still enabling the desired threshold differences through controlled dopant patterning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of doped and undoped high-k gate oxide structures in CMOS integrated circuits without degrading device properties, allowing for improved performance by minimizing dopant diffusion and oxygen impact on gate capacitance.
Implementation Method 1
using a multi-layered or single layered blocking stack as a buffer to prevent dopant migration
Implementation Method 2
minimize oxygen diffusion
Implementation Method 3
The use of selective etching of multi-layered stacks or controlled etching of single layered blocking stacks to form high-k replacement metal gate structures
Data Source
AI summary
A method of fabricating advanced node field effect transistors using a replacement metal gate process. The method includes dopant a high-k dielectric directly or indirectly by using layers composed of multi-layer thin film stacks, or in other embodiments, by a single blocking layer. By taking advantage of unexpected etch selectivity of the multi-layer stack or the controlled etch process of a single layer stack, etch damage to the high-k may be avoided and work function metal thicknesses can be tightly controlled which in turn allows field effect transistors with low Tinv (inverse of gate capacitance) mismatch.