Epitaxial High-K Etch Stop Layer for Backside Reveal Selectivity
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Solution Overview
Problem
Existing methods for revealing the backside of integrated circuit (IC) devices face challenges such as lattice mismatch, limited etch selectivity, high cost, and complexity, which hinder efficient access to the device layer from both sides of the IC.
Innovation Solution
A backside reveal method utilizing an epitaxial high-k etch stop layer is employed, which involves depositing this layer on a semiconductor substrate, forming an IC device layer, attaching a carrier substrate, and selectively etching to expose the backside of the IC device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional backside reveal methods are used, then the device layer can be accessed from the backside, but lattice mismatch and limited etch selectivity occur
Solution Approach 1:
An epitaxial high-k etch stop layer is introduced as an intermediary between the semiconductor substrate and the integrated circuit device layer. This intermediate layer provides excellent etch selectivity for backside reveal while maintaining good lattice matching with the underlying substrate, thereby resolving the contradiction between etch selectivity and lattice mismatch.
Solution Approach 2:
The patent changes the material parameter by using high-k materials (such as HfO2, ZrO2, or their alloys) with specific dielectric constants and lattice constants. These parameter changes enable both high etch selectivity and good lattice matching, simultaneously improving reliability and manufacturing precision.
2Ease of operation
If existing backside reveal methods are employed, then access to device layer is achieved, but process complexity and cost increase
Solution Approach 1:
The epitaxial high-k etch stop layer is deposited on the semiconductor substrate before forming the integrated circuit device layer. This preliminary action simplifies subsequent backside reveal processes by providing a pre-established etch stop reference, reducing overall process complexity while maintaining ease of operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively addresses the challenges of lattice mismatch and etch selectivity, enabling efficient backside access while reducing costs and complexity, thus facilitating 3D integration of logic technology with memory or other devices.
Implementation Method 1
depositing an epitaxial high-k etch stop layer on the semiconductor material substrate
Implementation Method 2
removing, by a first selective etching, the remaining portion of the semiconductor material substrate
Implementation Method 3
removing, by a second selective etching, the epitaxial high-k etch stop layer to expose a backside of the integrated circuit device
Data Source
AI summary
A backside reveal method includes providing a semiconductor material substrate, depositing an epitaxial high-k etch stop layer on the semiconductor material substrate, forming an integrated circuit device layer on the epitaxial high-k etch stop layer, and attaching a carrier substrate to a front side of the integrated circuit device layer. The method further includes removing a portion of a thickness of the semiconductor material substrate to leave a remaining portion of the thickness of the semiconductor material substrate, removing, by a first selective etching, the remaining portion of the semiconductor material substrate, and removing, by a second selective etching, the epitaxial high-k etch stop layer to expose a backside of the integrated circuit device layer. The epitaxial high-k etch stop layer has good lattice match and high etch selectivity relative to the semiconductor material substrate.