Selective High-k Gate Dielectric Layout for Low-Capacitance GAA Channels
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Solution Overview
Problem
Conventional fabrication processes for multi-gate transistors, such as tri-gate and gate-all-around (GAA) transistors, face challenges in scaling to smaller dimensions due to variability and increased parasitic capacitance, which affects device performance and switching speed.
Innovation Solution
Implementing a selective deposition process to omit vertical portions of the gate dielectric layer on spacers in GAA transistors, using a liner to prevent deposition on spacer surfaces, thereby allowing for increased spacer width or gate metal volume, reducing parasitic capacitance and improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate dielectric layer is deposited over all surfaces including spacers, then complete coverage is achieved, but parasitic capacitance increases and device performance deteriorates
Solution Approach 1:
The patent applies local quality by making the gate dielectric deposition selective to specific locations. The liner layer is deposited only on the spacer surfaces to prevent dielectric deposition, while the channel surfaces receive the gate dielectric. This localized differentiation reduces parasitic capacitance at the spacer regions while maintaining necessary dielectric coverage on the channels, thereby improving device performance without complete coverage.
Solution Approach 2:
The liner layer acts as an intermediary substance between the spacer and the gate dielectric deposition process. This intermediate layer prevents the gate dielectric from depositing on the spacer surfaces, effectively mediating the selective deposition process. The liner material (such as silicon nitride or silicon carbide) serves as a barrier that blocks dielectric formation on spacers, reducing parasitic capacitance while allowing the gate dielectric to form on the channel surfaces.
2Object-affected harmful factors
If spacer width is increased to reduce parasitic capacitance, then available space for gate metal is reduced, but gate resistance increases
Solution Approach 1:
The patent segments the deposition process into two distinct regions: the spacer surfaces covered by the liner layer where no gate dielectric forms, and the channel surfaces where the gate dielectric is deposited. This segmentation allows the spacer width to be optimized for reducing parasitic capacitance without compromising gate metal volume, as the gate dielectric is selectively absent from the spacer regions. The space between channels is thus efficiently utilized for both spacer function and gate metal placement.
Solution Approach 2:
By applying the liner layer locally on spacers, the patent creates a local quality difference that enables selective gate dielectric deposition. This local modification allows the spacer width to be increased in specific regions without reducing the overall gate metal volume, as the gate dielectric is absent only where the liner is present. The result is reduced parasitic capacitance from wider spacers while maintaining adequate gate metal volume for low resistance.
3Object-affected harmful factors
If selective deposition is implemented using a liner layer, then parasitic capacitance is reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent applies preliminary action by depositing the liner layer on the spacer surfaces before the gate dielectric deposition step. This pre-coating of the spacers with a deposition-blocking material ensures that when the gate dielectric is subsequently deposited, it will not form on the spacer surfaces. This preliminary protective measure simplifies the overall process by preventing unwanted dielectric formation in one step, rather than requiring complex masking or post-processing removal techniques.
Solution Approach 2:
The liner layer serves as an intermediary that simplifies the manufacturing process by enabling selective deposition without complex masking. Instead of using photolithography masks or complex deposition control mechanisms, the liner material (such as silicon nitride or silicon carbide) acts as a simple, effective barrier that prevents gate dielectric deposition on spacers. This intermediary approach reduces process complexity compared to alternative methods that would require multiple steps or sophisticated control systems.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces parasitic capacitance and gate resistance, enhancing switching frequency and overall device performance by optimizing the use of space between semiconductor channels.
Implementation Method 1
using a liner to prevent deposition on spacer surfaces
Implementation Method 2
Implementing a selective deposition process that omits vertical portions of the gate dielectric layer on spacers
Data Source
AI summary
Embodiments disclosed herein include transistor devices and methods of forming such devices. In an embodiment, a transistor device comprises a first channel, wherein the first channel comprises a semiconductor material and a second channel above the first channel, wherein the second channel comprises the semiconductor material. In an embodiment, a first spacer is between the first channel and the second channel, and a second spacer is between the first channel and the second channel. In an embodiment, a first gate dielectric is over a surface of the first channel that faces the second channel, and a second gate dielectric is over a surface of the second channel that faces the first channel. In an embodiment, the first gate dielectric is physically separated from the second gate dielectric.