High-K Gate Dielectric Annealing for Low Diffusion FinFET Gates
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in minimizing gate dielectric loss and dopant diffusion during metal gate patterning, particularly due to the limitations in crystallization and annealing temperatures, which affect the integration density and performance of FinFETs.
Innovation Solution
The method involves depositing a gate dielectric layer along the sidewalls and top surface of a fin, followed by microsecond annealing at temperatures between 1000° C to 1150° C to enhance crystallization and reduce dopant diffusion, allowing for higher annealing peak temperatures while minimizing drain-induced barrier lowering effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional annealing processes are used during metal gate patterning, then gate dielectric loss is reduced, but dopant diffusion increases and crystallization is insufficient
Solution Approach 1:
The patent applies rapid thermal annealing (RTA) with a temperature ramp rate of at least 100°C per second, heating to a peak temperature between 700°C and 1100°C and maintaining it for 1 second to 10 minutes. This parameter change enables sufficient crystallization of the gate dielectric layer while minimizing dopant diffusion, resolving the contradiction between reducing gate dielectric loss and controlling dopant diffusion.
2Strength
If higher annealing peak temperatures are used to improve crystallization, then gate dielectric strength increases, but dopant diffusion and drain-induced barrier lowering effects worsen
Solution Approach 1:
The patent employs periodic rapid thermal annealing cycles with controlled peak temperatures between 700°C and 1100°C maintained for 1 second to 10 minutes, followed by rapid cooling. This periodic action allows the gate dielectric to achieve sufficient crystallization and strength while the brief exposure time at high temperature minimizes dopant diffusion and drain-induced barrier lowering effects.
3Manufacturing precision
If conventional annealing temperatures are used, then dopant diffusion is minimized, but gate dielectric crystallization and strength are insufficient
Solution Approach 1:
The patent implements rapid thermal annealing with a minimum temperature ramp rate of 100°C per second, achieving peak temperatures between 700°C and 1100°C and maintaining them for 1 second to 10 minutes. This parameter change enables the gate dielectric to achieve sufficient crystallization and strength while the rapid heating and cooling minimize dopant diffusion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a stronger gate dielectric layer with reduced loss during metal gate patterning, improved crystallinity, and lower risk of performance degradation, enabling higher integration density and better device performance.
Implementation Method 1
performing a first annealing process on the first high-k dielectric layer; performing a second annealing process on the first high-k dielectric layer and the second high-k dielectric layer
Implementation Method 2
after the second annealing process the first high-k dielectric layer and the second high-k dielectric layer have a combined crystallinity that is higher than 70 percent
Data Source
AI summary
A method includes depositing a first high-k dielectric layer over a first semiconductor region, performing a first annealing process on the first high-k dielectric layer, depositing a second high-k dielectric layer over the first high-k dielectric layer; and performing a second annealing process on the first high-k dielectric layer and the second high-k dielectric layer.