High-k Gate Insulation Layout to Cut Parasitic Capacitance
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Solution Overview
Problem
There is a need for semiconductor devices with improved electrical and reliability characteristics, particularly in terms of low power consumption and high integration density, which existing semiconductor devices have not adequately addressed.
Innovation Solution
A semiconductor device design incorporating a substrate with an active pattern, a gate electrode, a gate spacer, an inhibition layer, and a gate insulating layer that includes a high-k dielectric layer and a gate oxide layer, where the high-k dielectric layer is locally provided between the gate oxide layer and the gate electrode, with varying thicknesses to reduce parasitic capacitance and internal leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the high-k dielectric layer is extended between the inhibition layer and the side of the gate electrode, then the gate insulating layer provides better insulation, but parasitic capacitance increases and internal leakage current occurs
Solution Approach 1:
The patent extracts the high-k dielectric layer from the region between the inhibition layer and the gate electrode side, removing only the harmful portion while retaining the beneficial insulation function in other areas. This selective removal eliminates parasitic capacitance and internal leakage current pathways.
Solution Approach 2:
The high-k dielectric layer is provided locally in specific regions (between the gate electrode and active pattern, and between the gate electrode and source/drain patterns) but intentionally omitted in the critical region between the inhibition layer and gate electrode side. This local differentiation optimizes insulation where needed while avoiding harmful capacitance effects.
2Reliability
If the high-k dielectric layer is made thicker to improve insulation, then gate insulation performance improves, but parasitic capacitance increases
Solution Approach 1:
The patent applies different thickness characteristics of the high-k dielectric layer in different spatial locations. The layer is thicker in regions requiring strong insulation (between gate and active pattern) while being thinner or absent in regions where it would generate parasitic capacitance (between inhibition layer and gate side), achieving localized optimization of the thickness parameter.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves low power consumption and improved reliability by reducing parasitic capacitance and internal leakage current, enhancing the overall performance and integration density of semiconductor devices.
Implementation Method 1
a gate insulating layer between the gate electrode and the active pattern. The gate insulating layer may include a high-k dielectric layer and a gate oxide layer
Implementation Method 2
The gate oxide layer may be between the high-k dielectric layer and the active pattern
Data Source
AI summary
Disclosed are a semiconductor device and a method of fabricating the same. The device may include a substrate, an active pattern in an upper portion of the substrate and is extending in a first direction, a gate electrode crossing the active pattern and extending in a second direction intersecting the first direction, a first gate spacer covering a side surface of the gate electrode, a first inhibition layer between the gate electrode and the first gate spacer, and a gate insulating layer between the gate electrode and the active pattern. The gate insulating layer may include a high-k dielectric layer and a gate oxide layer. The gate oxide layer may be between the high-k dielectric layer and the active pattern. The high-k dielectric layer may be between the gate oxide layer and the gate electrode.