High-k Gate Capping for Germanium Oxide Defect Reduction
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Solution Overview
Problem
The formation of high-quality gate dielectric layers in advanced transistors, such as FinFET and gate-all-around transistors, is challenged by the instability of germanium oxide in the interfacial oxide layer, which can lead to defects and affect device performance.
Innovation Solution
A method involving the deposition of a high-k gate dielectric layer followed by a metal nitride layer, treated with a metal-containing gas to form a metal intermixing layer, and subsequent rapid thermal annealing to reduce germanium oxide content, enhancing the quality of the interfacial oxide layer and high-k gate dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If germanium oxide is present in the interfacial oxide layer, then the gate dielectric layer can be formed, but the germanium oxide instability causes defects and reduces device performance
Solution Approach 1:
The patent extracts and removes germanium oxide from the interfacial oxide layer through selective etching processes. The metal-containing gas treatment selectively reacts with and removes germanium oxide while preserving silicon dioxide, thereby eliminating the unstable component that causes defects and improves device reliability.
Solution Approach 2:
The patent converts the harmful effect of germanium oxide instability into a benefit by using metal-containing gases (such as tungsten hexafluoride or molybdenum tetroxide) that selectively react with germanium oxide. The metal atoms replace germanium atoms in the oxide layer, and subsequent annealing forms stable metal oxide clusters that actually improve the interfacial quality and reduce defects.
2Manufacturing precision
If a metal-containing gas treatment and rapid thermal annealing are performed, then the germanium oxide content is reduced and quality is enhanced, but the process complexity increases
Solution Approach 1:
The patent applies metal-containing gas treatment as a preliminary step before final gate dielectric formation. This pre-treatment modifies the interfacial oxide layer in advance, removing germanium oxide and preparing a cleaner interface, which simplifies subsequent processing steps and ensures higher quality outcomes.
Solution Approach 2:
The patent utilizes rapid thermal annealing with specific temperature parameters (typically 400-600°C for short durations) to control the chemical reactions. By precisely controlling temperature and time parameters, the process achieves selective removal of germanium oxide while preserving the desired oxide composition, thereby improving quality through parameter optimization rather than adding complex process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method improves the quality of the interfacial oxide layer and high-k gate dielectric layers, reducing defects and enhancing the performance of p-type MOSFETs, particularly in multi-gate devices like FinFET and gate-all-around transistors.
Implementation Method 1
performing a first treatment to the structure using a metal-containing gas... a metal intermixing layer is formed over the high-k gate dielectric layer, wherein the metal intermixing layer includes a metal oxide having metal species from the high-k gate dielectric layer and additional metal species from the metal-containing gas
Implementation Method 2
after the depositing of the silicon layer, annealing the structure such that a metal intermixing layer is formed over the high-k gate dielectric layer
Implementation Method 3
the metal intermixing layer includes a metal oxide having metal species from the high-k gate dielectric layer and additional metal species from the metal-containing gas
Data Source
AI summary
A semiconductor structure includes a semiconductor channel member, a germanium-rich semiconductor layer over the semiconductor channel member, an interfacial layer over the germanium-rich semiconductor layer, a gate dielectric layer over the interfacial layer, and a gate electrode layer over the gate dielectric layer. The germanium-rich semiconductor layer includes a higher germanium content than the semiconductor channel member.