High-k Gate Dielectric Concentration Zoning for Threshold Voltage Control
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Solution Overview
Problem
Current semiconductor devices with high-k gate dielectric layers face challenges in achieving optimal threshold voltages due to variations in dipole material concentrations across different areas, leading to inconsistent performance across transistor types.
Innovation Solution
The semiconductor device incorporates high-k gate dielectric layers with varying concentrations of N-type and P-type dipole materials in specific areas, with higher concentrations in some layers to achieve targeted threshold voltages through an annealing process, allowing for tailored threshold voltage control across different transistor types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If uniform dipole material concentration is used across all gate structures, then manufacturing process is simple, but threshold voltage control precision is poor
Solution Approach 1:
The patent applies local quality by forming dipole material layers with different concentrations in different gate structures. Specifically, a first dipole material layer with first concentration is formed for first gate structures, and a second dipole material layer with second concentration is formed for second gate structures, enabling precise threshold voltage control tailored to each transistor type's requirements
Solution Approach 2:
The patent segments the dipole material formation process into distinct steps for different gate structures. The method separates the formation of dipole material layers into at least two different dipole material layers with different concentrations, allowing independent optimization of threshold voltages for NMOS and PMOS transistors
2Adaptability or versatility
If high-k gate dielectric layer with dipole materials is used, then threshold voltage adjustment capability is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent applies preliminary action by forming dipole material layers during the gate dielectric formation process itself, rather than as a separate subsequent step. The dipole material layers are formed on the high-k gate dielectric layer before completing the gate electrode structure, enabling threshold voltage adjustment to be built into the base process flow
Solution Approach 2:
The patent merges the threshold voltage adjustment function with the gate dielectric layer formation process. By integrating dipole material layer formation into the high-k gate dielectric fabrication sequence, the patent combines multiple functions (dielectric formation and threshold voltage control) into a unified process structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise control of threshold voltages, resulting in improved performance and efficiency across various transistor types by optimizing dipole material concentrations within the high-k gate dielectric layers.
Implementation Method 1
diffusing an N-type dipole material in the N-type dipole material layer into the high-k gate dielectric layer in the first and third areas and diffusing a P-type dipole material in the P-type dipole material layer into the high-k gate dielectric layer in the second and fourth areas by performing an annealing process
Implementation Method 2
by performing an annealing process
Data Source
AI summary
A semiconductor device includes a first gate structure including a first N-type high-k gate dielectric layer, a second gate structure comprising a first P-type high-k gate dielectric layer, a third gate structure including a second N-type high-k gate dielectric layer, and a fourth gate structure including a second P-type high-k gate dielectric layer. The first N-type high-k gate dielectric layer includes an N-type dipole material with a first concentration. The first P-type high-k gate dielectric layer includes a P-type dipole material with a second concentration. The second N-type high-k gate dielectric layer includes the N-type dipole material with a third concentration. The second P-type high-k gate dielectric layer includes the P-type dipole material with a fourth concentration. The first concentration is higher than the third concentration, and the second concentration is higher than the fourth concentration.