High-K Gate Dielectric Dipole Diffusion for Threshold Voltage Tuning

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Solution Overview

Problem

The shrinking geometry of semiconductor IC devices complicates the formation of desirable shapes in gate trenches, particularly in gate-last processes, as additional dipole layers and dielectric layers reduce the process window for depositing the functional metal gate structure, especially when the gate trench is not straight.

Innovation Solution

A method involving the deposition of a gate dielectric layer and selective deposition and removal of dipole layers over the gate dielectric in specific device regions, followed by annealing to diffuse dopants into the gate dielectric, allowing for the formation of transistors with different threshold voltages without narrowing the process window.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If additional dipole layers and dielectric layers are deposited over the gate dielectric layer to provide transistors with different threshold voltages, then the threshold voltage control is improved, but the process window for depositing the functional metal gate stack is reduced

Engineering Contradiction:
Improvethreshold voltage controlVSAvoidprocess window
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent extracts the dipole layers from the gate trench structure after they have served their purpose as diffusion vehicles. By removing the dipole layers after threshold voltage adjustment, the gate trench is cleared for subsequent functional metal gate stack deposition, thereby resolving the conflict between threshold voltage control and process window availability

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The dipole layers serve as temporary intermediary structures that facilitate threshold voltage control during fabrication. They act as diffusion vehicles for dopants and are subsequently removed, allowing the functional metal gate stack to be deposited without interference, thus mediating between threshold voltage requirements and manufacturing ease

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If the gate trench dimensions are reduced due to shrinking geometry, then the device scaling is improved, but the process window for depositing the functional metal gate stack is further reduced

Engineering Contradiction:
Improvedevice scalingVSAvoidprocess window
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

By removing the dipole layers after they have served as diffusion vehicles, the patent eliminates obstacles in the gate trench that would otherwise interfere with functional metal gate stack deposition. This extraction approach maintains adequate process window even in scaled-down gate trench dimensions

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The dipole layers are deposited preliminarily before the functional metal gate stack to enable threshold voltage control. After serving their purpose, they are removed to clear the way for subsequent deposition, allowing scaling to proceed without compromising the process window for functional gate formation

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the formation of transistors with varying threshold voltages while maintaining a consistent and expanded process window for the functional metal gate stack, improving the fabrication process by using dipole layers as diffusion vehicles rather than permanent components in the gate trench.

Implementation Method 1

annealing to diffuse dopants into the gate dielectric

Methodology Applied
Scientific EffectDiffusion: Diffusion

Data Source

PatentUS11862706B2High-K gate dielectric
Publication Date: 2024.01.02 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11862706B2 patent drawing
  • US11862706B2 patent drawing
  • US11862706B2 patent drawing

AI summary

Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first transistor having a first gate dielectric layer, a second transistor having a second gate dielectric layer, and a third transistor having a third gate dielectric layer. The first gate dielectric layer includes a first concentration of a dipole layer material, the second gate dielectric layer includes a second concentration of the dipole layer material, and the third gate dielectric layer includes a third concentration of the dipole layer material. The dipole layer material includes lanthanum oxide, aluminum oxide, or yttrium oxide. The first concentration is greater than the second concentration and the second concentration is greater than the third concentration.