High-K Gate Dielectric Interfacial Layer Structure
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Solution Overview
Problem
As semiconductor devices become more highly integrated, the short channel effect in MOS transistors becomes a challenge due to the degradation of interfacial characteristics between the semiconductor substrate and high-k dielectric layers, leading to increased gate leakage current and reliability issues.
Innovation Solution
A method is introduced where a nitride layer is formed as an oxidation blocking layer on the semiconductor substrate and layer, followed by an oxide layer and a high-k dielectric layer, using remote plasma nitrification and CVD processes, to create an interfacial structure that minimizes oxidation and enhances interface characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high-k dielectric layer is formed directly on the semiconductor substrate, then the dielectric constant is increased to reduce gate leakage, but the interfacial characteristics degrade leading to reliability issues
Solution Approach 1:
A nitride interfacial layer is introduced as an intermediary between the semiconductor substrate and the high-k dielectric layer. This nitride layer prevents direct contact between the high-k dielectric and semiconductor substrate, maintaining clean interfacial characteristics while still allowing the high-k dielectric to provide gate leakage reduction.
Solution Approach 2:
The gate stack is formed as a composite structure combining multiple materials: semiconductor substrate, nitride interfacial layer, and high-k dielectric layer. This composite approach allows each layer to perform its optimal function - the nitride layer protects the interface while the high-k dielectric reduces gate leakage.
2Productivity
If the channel length is decreased to achieve higher integration, then the device density is increased, but the short channel effect becomes more severe
Solution Approach 1:
The dielectric constant parameter is changed by introducing high-k dielectric material. This allows the gate to maintain effective control over the channel even at reduced lengths, counteracting the short channel effect while enabling higher integration through smaller device dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains consistent equivalent oxide thickness across N-channel and P-channel MOS transistors, optimizing electrical characteristics and reducing gate leakage, thereby addressing the short channel effect and improving reliability.
Implementation Method 1
nitrifying an exposed surface of the semiconductor substrate to form a first nitride interfacial layer
Implementation Method 2
The oxidation blocking layer may be formed using a remote plasma nitrification process
Implementation Method 3
The intermediate interfacial layer may be formed using an oxygen gas and ultraviolet radiation
Data Source
AI summary
A method of fabricating a semiconductor device includes forming a lower interfacial layer on a semiconductor layer, the lower interfacial layer being a nitride layer, forming an intermediate interfacial layer on the lower interfacial layer, the intermediate interfacial layer being an oxide layer, and forming a high-k dielectric layer on the intermediate interfacial layer. The high-k dielectric layer has a dielectric constant that is higher than dielectric constants of the lower interfacial layer and the intermediate interfacial layer.