High-K Gate Dielectric Layering for Leakage and Mobility
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Solution Overview
Problem
Thin gate insulating films in MOSFETs lead to high gate leakage current, mobility degradation, and patterning difficulties with high-K gate dielectrics like hafnium oxide, which increases power consumption and damages semiconductor materials.
Innovation Solution
Forming multiple thickness and composition high-K gate dielectric layers by depositing high-K atoms over a conventional gate dielectric and subjecting the structure to heat treatment, allowing for tailored dielectric constants and reduced patterning needs, thereby suppressing gate leakage and mitigating mobility degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If thin gate insulating films are used to increase operation speed, then operation speed is improved, but gate leakage current increases
Solution Approach 1:
The patent uses a composite gate dielectric structure consisting of silicon dioxide and high-k material layers. The silicon dioxide layer provides good interface quality and low leakage, while the high-k material layer provides high dielectric constant for voltage control. This composite structure enables thin effective oxide equivalent thickness for high speed operation while maintaining low actual physical thickness to reduce gate leakage current.
Solution Approach 2:
The patent creates different regions with different dielectric thicknesses within the same gate structure. By having varying local thicknesses of the high-k material layer, the gate can be optimized for different regions - thinner in areas requiring high speed and thicker in areas requiring low leakage, thus resolving the contradiction between speed and leakage at different locations.
2Object-generated harmful factors
If high-K gate dielectrics are used to reduce gate leakage, then gate leakage is reduced, but mobility degradation occurs
Solution Approach 1:
The patent creates a graded interface structure where the high-k material concentration varies spatially. By having a lower concentration of high-k material near the silicon interface and higher concentration away from it, the interface quality is maintained for good carrier mobility while still achieving high effective dielectric constant for low gate leakage current.
Solution Approach 2:
The patent controls the composition and thickness parameters of the high-k material layer to optimize the balance between leakage reduction and mobility maintenance. By adjusting the dielectric constant, physical thickness, and interface quality parameters, the gate structure achieves low gate leakage while minimizing carrier mobility degradation.
3Ease of manufacture
If strong acid is used for patterning high-K gate dielectrics, then patterning is achieved, but semiconductor device materials are damaged
Solution Approach 1:
The patent introduces a sacrificial layer or mask structure that acts as an intermediary during patterning. This intermediary layer protects the underlying semiconductor device materials from strong acid damage while allowing the high-k gate dielectric to be patterned. The sacrificial layer is removed after patterning, leaving the desired pattern without material damage.
Solution Approach 2:
The patent uses a multi-layer patterning approach where a pattern is first formed in a resistant layer that is then transferred to the high-k dielectric. This copying process allows pattern transfer without direct exposure of sensitive semiconductor materials to strong acids, thus achieving patterning capability while avoiding material damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces gate leakage current and mobility degradation while avoiding damage to semiconductor materials, enabling the fabrication of microelectronic devices with improved performance and reduced power consumption.
Implementation Method 1
forming a layer of high-K atoms over the conventional gate dielectric
Implementation Method 2
heating the structure to form a high-K gate dielectric layer having multiple thicknesses and/or multiple compositions
Data Source
AI summary
Disclosed are methods of making an integrated circuit with multiple thickness and/or multiple composition high-K gate dielectric layers and integrated circuits containing multiple thickness and/or multiple composition high-K gate dielectrics. The methods involve forming a layer of high-K atoms over a conventional gate dielectric and heating the layer of high-K atoms to form a high-K gate dielectric layer. Methods of suppressing gate leakage current while mitigating mobility degradation are also described.