High-k Metal Gate Lanthanum Doping for FinFET Threshold Tuning
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Solution Overview
Problem
Conventional polysilicon gates in MOS devices experience poly-depletion effects, leading to increased effective gate dielectric thickness and difficulty in creating an inversion layer, which is not effectively addressed by existing metal gate technologies for tuning threshold voltages in FinFETs.
Innovation Solution
A doping-metal-containing layer, potentially comprising lanthanum, is selectively formed on high-k dielectric layers in specific transistor regions, with a hard mask patterned to remove the doping metal from one region while driving it into the other, allowing for selective adjustment of threshold voltages through an anneal process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional polysilicon gates are used in MOS devices, then the gate structure is simple and easy to manufacture, but poly-depletion effects occur leading to increased effective gate dielectric thickness and difficulty in creating inversion layers
Solution Approach 1:
The patent changes the material parameter of the gate from conventional polysilicon to metal materials with different work functions. By selecting metals with appropriate work functions (e.g., tungsten for PMOS, titanium nitride for NMOS), the threshold voltage and electrical characteristics are optimized to eliminate poly-depletion effects while maintaining ease of manufacture through standard metal deposition processes
Solution Approach 2:
The patent employs composite gate structures combining multiple metal layers with different properties. For example, a stack of tungsten, titanium nitride, and tantalum nitride layers creates a composite gate that simultaneously achieves low resistance, appropriate work function, and stability, resolving the contradiction between manufacturing simplicity and device performance
2Adaptability or versatility
If metal gates with multiple layers are formed to meet different requirements of NMOS and PMOS devices, then threshold voltage tuning capability is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent segments the gate structure into functionally distinct layers: a bottom metal layer for mechanical support and adhesion, an intermediate work function control layer for threshold voltage tuning, and a top capping layer for protection. This segmentation allows independent optimization of each layer's thickness and material properties to achieve desired threshold voltages for both NMOS and PMOS devices
Solution Approach 2:
The patent applies local quality by using different metal materials and thicknesses in different regions of the gate stack. For instance, titanium nitride layers are selectively applied in NMOS regions while tungsten dominates in PMOS regions, allowing localized threshold voltage control without complicating the overall manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables precise tuning of threshold voltages in FinFETs by selectively doping the high-k dielectric layers, improving the formation of inversion layers and addressing poly-depletion effects, thereby enhancing the performance of MOS devices.
Implementation Method 1
performing an anneal to drive the doping metal in the doping-metal-containing layer into the first high-k dielectric layer
Data Source
AI summary
A method includes forming a first gate dielectric and a second gate dielectric over a first semiconductor region and a second semiconductor region, respectively, depositing a lanthanum-containing layer including a first portion and a second portion overlapping the first gate dielectric and the second gate dielectric, respectively, and depositing a hard mask including a first portion and a second portion overlapping the first portion and the second portion of the lanthanum-containing layer, respectively. The hard mask is free from both of titanium and tantalum. The method further includes forming a patterned etching mask to cover the first portion of the hard mask, with the second portion of the hard mask being exposed, removing the second portion of the hard mask and the second portion of the lanthanum-containing layer, and performing an anneal to drive lanthanum in the first portion of the lanthanum-containing layer into the first gate dielectric.