High-k Gate Stack Fluorine Doping for Low-Leakage Transistors
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Solution Overview
Problem
Transistors in semiconductor devices face challenges with high leakage current and low on-current due to defects in the gate insulation layer, which affect their electrical properties.
Innovation Solution
Incorporating a gate insulation pattern with a high dielectric constant and doping it with fluorine-based dopants to cure defects, along with a threshold voltage controlling metal pattern and a conductive pattern to enhance electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate insulation layer is used, then the device structure is simple, but leakage current increases due to defects
Solution Approach 1:
The gate insulation layer is divided into multiple sub-layers (first gate insulation layer, second gate insulation layer, third gate insulation layer) with different materials and functions. This segmentation allows each layer to address specific defects and achieve better overall reliability while managing complexity through functional specialization.
Solution Approach 2:
The patent employs composite gate insulation structure combining different materials (silicon oxide, silicon nitride, silicon oxynitride) in a stacked configuration. Each material contributes specific properties that collectively reduce leakage current and address defects, achieving high reliability through material composition rather than single-material solutions.
2Reliability
If the gate insulation layer has defects, then manufacturing is easier, but on-current decreases due to poor electrical properties
Solution Approach 1:
The patent applies preliminary treatments to the gate insulation layers including defect curing processes and interface preparation before final device assembly. These beforehand actions prevent defect propagation and ensure high electrical properties, achieving high on-current through proactive quality assurance in the manufacturing process.
Solution Approach 2:
The patent optimizes multiple parameters of the gate insulation structure including layer thicknesses, material compositions, and doping concentrations. By carefully adjusting these parameters, the structure achieves optimal electrical properties for high on-current while maintaining manufacturability through controlled parameter ranges.
3Reliability
If a simple gate structure is used, then device complexity is low, but electrical properties are insufficient
Solution Approach 1:
Different regions of the gate structure have specialized properties tailored to local requirements. The gate insulation layers have varying materials and thicknesses at different positions, and doping is applied selectively to specific regions. This local quality approach achieves superior overall electrical properties while keeping each local section relatively simple and manufacturable.
Solution Approach 2:
The gate structure employs a nested configuration where multiple gate insulation layers are stacked within each other, with each layer contained within the overall gate structure. This nesting approach achieves complex electrical properties through layered composition while maintaining a unified and manageable structural framework.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces leakage current and increases on-current by effectively addressing defects in the gate insulation layer, thereby improving the transistor's electrical performance.
Implementation Method 1
The gate insulation pattern may include an oxide having a dielectric constant higher than that of silicon oxide
Implementation Method 2
First dopants may be present within and at at least one surface of the gate insulation pattern and at an upper surface of the interface insulation pattern contacting the gate insulation pattern. The first dopants may include at least fluorine.
Data Source
AI summary
A semiconductor device may include a substrate, an interface insulation pattern, a gate insulation pattern, a threshold voltage controlling metal pattern and a conductive pattern. The interface insulation pattern may be formed on the substrate. The gate insulation pattern including an oxide having a dielectric constant higher than that of silicon oxide may be formed on the interface insulation pattern. The threshold voltage controlling metal pattern may be formed on the gate insulation pattern. The conductive pattern may be formed on the threshold voltage controlling metal pattern. First dopants including at least fluorine may be included within and at at least one surface of the gate insulation pattern and at an upper surface of an interface insulation pattern contacting the gate insulation pattern. The semiconductor device may have excellent electrical characteristics.