High-k Gate Dielectric Fluorine Passivation via Dummy Metal
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving reliable and uniform gate dielectric quality in high-k/metal gate structures for field-effect transistors, particularly due to defects like oxygen vacancies that affect threshold voltage and reliability.
Innovation Solution
A method is developed to form a semiconductor device with a high-k gate dielectric layer, where a dummy metal layer with fluorine is deposited over the high-k dielectric, and a high temperature process drives fluorine into the gate dielectric to passivate oxygen vacancies, followed by removal of the dummy layer and formation of work function metal layers and a fill metal layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional polysilicon gates are replaced with high-k/metal gates, then transistor density and switching speed are improved, but gate dielectric quality and reliability deteriorate due to defects like oxygen vacancies
Solution Approach 1:
A dummy metal layer containing fluorine is deposited over the high-k gate dielectric layer before the final gate structure is completed. This preliminary action allows fluorine to be introduced into the gate dielectric to passivate oxygen vacancies and improve dielectric quality, while the dummy layer is later removed to form the final high-k/metal gate structure with improved reliability
2Loss of energy
If high-k gate dielectric layer is used, then switching power and gate leakage are reduced, but uniformity and reliability of gate dielectric deteriorate due to oxygen vacancies
Solution Approach 1:
The chemical composition of the gate dielectric is modified by introducing fluorine through the dummy metal layer. This parameter change passivates oxygen vacancies in the high-k gate dielectric, improving uniformity and reducing defects while maintaining the low leakage properties of the high-k material
3Reliability
If dummy metal layer with fluorine is deposited and high temperature process is performed, then gate dielectric reliability is improved through passivation, but process complexity increases
Solution Approach 1:
A dummy metal layer containing fluorine is used as an intermediary to deliver fluorine to the high-k gate dielectric. This intermediary approach allows controlled introduction of fluorine for passivation, and the dummy layer serves as a temporary vehicle that is later removed, achieving reliability improvement through a systematic multi-step process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the uniformity and reliability of the gate dielectric, reducing threshold voltage variations and improving the overall performance of the semiconductor device by passivating defects and allowing for simultaneous processing of PMOS and NMOS devices.
Implementation Method 1
a high temperature process is performed to drive the fluorine from the dummy metal layer into the high-k dielectric layer
Implementation Method 2
drive the fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer
Data Source
AI summary
A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer is formed over the high-k dielectric layer. The dummy metal layer includes fluorine. A high temperature process is performed to drive the fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer. Thereafter, the dummy metal layer is removed. At least one work function layer over the passivated high-k dielectric layer is formed. A fill metal layer is formed over the at least one work function layer.