High-K Metal Gate Lanthanum Doping for Threshold Voltage Tuning
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Solution Overview
Problem
The poly-depletion effect in metal-oxide-semiconductor (MOS) devices, where depletion layers form in gate regions, increasing the effective gate dielectric thickness and making it difficult to create an inversion layer, is not adequately addressed by conventional methods.
Innovation Solution
A doping-metal-containing layer, such as lanthanum, is selectively applied to a high-k dielectric layer in one transistor region to adjust its threshold voltage, while leaving another region unchanged, using a hard mask and anneal process to drive the doping metal into the dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional polysilicon gates are used, then the device structure is simple, but the poly-depletion effect increases the effective gate dielectric thickness making it difficult to create an inversion layer
Solution Approach 1:
The patent extracts the problematic poly-depletion effect by replacing polysilicon gates with metal gates. The metal gate material is removed from the gate region to eliminate the depletion layer formation, thereby preventing the increase in effective gate dielectric thickness and enabling reliable inversion layer creation.
Solution Approach 2:
The patent employs composite metal gate structures consisting of multiple metal layers with different work functions. This composite approach allows optimization of both the inversion layer formation and the overall device performance by combining materials with complementary properties.
2Adaptability or versatility
If metal gates with multiple layers are formed to meet different NMOS and PMOS requirements, then the threshold voltage tuning capability is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent applies local quality by selectively doping different regions of the metal gate with specific metals (e.g., tungsten, molybdenum, niobium) at controlled concentrations. This allows each region of the gate to have tailored electrical properties, enabling independent optimization of NMOS and PMOS threshold voltages while using a unified gate structure.
Solution Approach 2:
The patent changes the physical and chemical parameters of the metal gate by controlling the concentration and distribution of dopant metals within the gate structure. By adjusting dopant concentration, distribution depth, and metal composition, the threshold voltage can be precisely tuned to meet different circuit requirements without changing the fundamental gate architecture.
3Productivity
If selective doping is performed to tune threshold voltages in different transistor regions, then the performance optimization is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent segments the gate structure into distinct doped and undoped regions by using selective deposition or doping processes. This segmentation allows different transistor regions (e.g., NMOS vs PMOS) to receive tailored doping treatments, achieving the desired threshold voltage differentiation while maintaining clear process boundaries for manufacturing control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for selective tuning of threshold voltages in transistors, enhancing their performance by adjusting the voltage range between 0 mV and 150 mV, suitable for different circuit requirements on a single device die.
Implementation Method 1
performing an anneal process to drive the doping metal into the high-k dielectric layer
Data Source
AI summary
A method includes forming a first gate dielectric and a second gate dielectric over a first semiconductor region and a second semiconductor region, respectively, depositing a lanthanum-containing layer including a first portion and a second portion overlapping the first gate dielectric and the second gate dielectric, respectively, and depositing a hard mask including a first portion and a second portion overlapping the first portion and the second portion of the lanthanum-containing layer, respectively. The hard mask is free from both of titanium and tantalum. The method further includes forming a patterned etching mask to cover the first portion of the hard mask, with the second portion of the hard mask being exposed, removing the second portion of the hard mask and the second portion of the lanthanum-containing layer, and performing an anneal to drive lanthanum in the first portion of the lanthanum-containing layer into the first gate dielectric.