High-k Dielectric Gate Structure for Leakage Reduction
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Solution Overview
Problem
The continuous reduction in MOS gate size in semiconductor devices leads to issues such as substantial leakage currents due to quantum effects, incompatibility of high temperature annealing with metal gates and high-k dielectric structures, and challenges in reducing drain induced barrier lowering and gate-source/drain overlap capacitance, which affect switching speed and fabrication processes.
Innovation Solution
A process involving the formation of an insulating layer with patterned holes, a hard mask spacer layer, anisotropic etching to control spacer layer thickness, and subsequent deposition of high-k dielectric and metal layers, followed by chemical mechanical polishing to isolate individual gate structures, allowing for precise control of gate dimensions and reduced overlap capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the thickness of silicon dioxide insulator is reduced to continue scaling, then device size is reduced, but quantum effects cause substantial leakage currents
Solution Approach 1:
The patent changes the dielectric constant parameter by replacing silicon dioxide with high-k dielectric materials (such as hafnium oxide, tantalum oxide, or aluminum oxide) that have higher dielectric constants. This allows achieving the same capacitive coupling with greater thickness, thereby reducing quantum tunneling leakage while maintaining device performance.
Solution Approach 2:
The patent employs composite gate structures combining metal layers with high-k dielectric materials (metal-high-k dielectric composite). This composite approach enables precise control of electrical characteristics while maintaining physical thickness sufficient to prevent leakage currents through the insulator.
2Reliability
If high temperature annealing is performed after implantation, then dopant activation is improved, but metal gate and high-k dielectric structures are damaged
Solution Approach 1:
The patent forms the metal gate and high-k dielectric structures before performing ion implantation and annealing operations. By placing these sensitive structures last in the process sequence, they are protected from damage by subsequent high-temperature treatments, while still achieving proper dopant activation in the source and drain regions.
Solution Approach 2:
The patent divides the fabrication process into distinct stages: first forming the semiconductor structure with source/drain regions, then separately forming the high-k dielectric and metal gate layers in subsequent steps. This segmentation allows independent optimization of each component without mutual interference, protecting the metal gate from thermal damage.
3Speed
If transistor gate length is reduced to increase switching speed, then device speed is improved, but drain induced barrier lowering and overlap capacitance increase
Solution Approach 1:
The patent changes the dielectric constant parameter using high-k materials, which allows increasing the physical thickness of the gate dielectric while maintaining the same electrical capacitance. This effectively increases the gate control voltage, compensating for the reduced gate length and reducing drain induced barrier lowering effects.
4Manufacturing precision
If hole size is reduced to maintain gate dimensions, then gate precision is improved, but filling with gate metallization becomes increasingly difficult
Solution Approach 1:
The patent changes the physical and chemical parameters of the metallization filling process, including using low-pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD) techniques that enable conformal filling of high-aspect-ratio holes. The process parameters are optimized to ensure complete filling without voids or defects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables uniform gate dimensions, reducing leakage currents and overlap capacitance, improving filling of high-k dielectric and metal layers, and enhancing transistor switching speed by up to 50% and lowering drain induced barrier lowering by approximately 70 mV, thereby addressing the challenges faced in high-k dielectric last technology.
Implementation Method 1
the spacer layer is anisotropically etched to remove the portion of the spacer layer exposed at the bottom of each hole as well as the portion of the spacer layer on the upper surface of the insulating layer
Implementation Method 2
Chemical mechanical polishing is then performed to remove the bulk gate metal down to the insulating layer, thereby isolating individual NMOS and PMOS gate structures
Data Source
AI summary
In an illustrative embodiment, holes are formed in an insulating layer where the gates of NMOS and PMOS transistors are to be formed; and a hard mask spacer layer is formed on the exposed surfaces. Next, spacers are formed on the sidewalls of the holes by anisotropically etching the spacer layer to remove the portion of the spacer layer exposed at the bottom of each hole while leaving some of the spacer layer formed on the sidewalls of the holes. A high-k dielectric layer is then formed between the spacers; and a metal layer is formed on the high-k dielectric layer. Bulk metal layer is then formed on the metal layer. Chemical mechanical polishing is performed to remove the bulk gate metal down to the insulating layer, thereby isolating individual NMOS and PMOS gate structures.