High-k Dielectric Gate Structure Spacer Etch Protection
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Solution Overview
Problem
In semiconductor fabrication, the formation of spacers during the gate structure process often results in over-etching or undercut issues, leading to erosion of high-k dielectric layers and bottom barrier metals, which affects device performance.
Innovation Solution
A method involving the use of an interfacial layer with a wider horizontal width than the patterned high-k dielectric layer, where spacers are formed adjacent to the gate structure, with the second spacer's planar bottom surface being lower than the first spacer's, to protect the high-k dielectric and bottom barrier metal layers from etching gas during the spacer formation process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If spacers are formed during gate structure fabrication, then gate structure is defined, but over-etching occurs causing erosion of high-k dielectric and bottom barrier metal layers
Solution Approach 1:
An interfacial layer is introduced as an intermediary protective layer between the etching gas and the high-k dielectric/bottom barrier metal layers. This interfacial layer acts as a mediator that absorbs the harmful etching effect, preventing direct contact between the etching gas and the sensitive layers that would otherwise be eroded during spacer formation.
Solution Approach 2:
The interfacial layer is formed in advance before the spacer formation etching process. By preparing this protective layer beforehand, the patent prevents the harmful effects of over-etching before they can occur, ensuring that the high-k dielectric and bottom barrier metal layers remain intact during subsequent spacer formation.
2Ease of manufacture
If conventional polysilicon gate is used, then fabrication is simplified, but performance deteriorates due to boron penetration and depletion effect
Solution Approach 1:
The patent employs a composite gate structure consisting of multiple layers including high-k dielectric material and bottom barrier metal layers, replacing the conventional single-material polysilicon gate. This composite structure combines materials with different properties to achieve both electrical performance improvement (reducing boron penetration and depletion effects) and manufacturing feasibility.
3Reliability
If high-k metal gate is implemented, then device performance improves, but fabrication complexity increases due to additional protective layers
Solution Approach 1:
The interfacial layer serves multiple functions simultaneously: it acts as a protective barrier during spacer formation, provides a interface for subsequent processing steps, and maintains structural integrity throughout the fabrication process. This multi-functionality reduces the need for additional separate protective layers, thereby managing fabrication complexity while maintaining high-k metal gate performance benefits.
Data Source
AI summary
A semiconductor device includes an interfacial layer on a substrate and agate structure on the interfacial layer. Preferably, the gate structure includes a patterned high-k dielectric layer, the patterned high-k dielectric layer comprises a metal oxide layer, and a horizontal direction width of the patterned high-k dielectric layer and a horizontal direction width of the interfacial layer are different. The semiconductor device also includes a first spacer adjacent to the gate structure and on part of the interfacial layer and contacting a top surface of the interfacial layer and a second spacer on the sidewalls of the first spacer and the interfacial layer. Preferably, a planar bottom surface of the second spacer is lower than a planar bottom surface of the first spacer and extending along a same direction as the planar bottom surface of the first spacer.