High-k Metal Gate Stack With Diffusion Barrier for Spacer Etching
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Solution Overview
Problem
In the semiconductor industry, the fabrication of high-k metal transistors faces issues such as over-etching and undercut during the formation of spacers, leading to erosion of the high-k dielectric layer and bottom barrier metal, which affects device performance.
Innovation Solution
A method involving the formation of a substrate with defined regions, a bottom barrier metal layer, a work function metal layer, and a diffusion barrier layer, where the thickness of the bottom barrier metal layer on one region is less than on another, and a diffusion barrier layer is formed to contact the work function metal and bottom barrier metal layers, ensuring proper coverage and reducing etching-related issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional polysilicon gate is used, then fabrication process is simple, but boron penetration and depletion effect occur which reduces gate capacitance and driving force
Solution Approach 1:
The patent uses a composite gate structure consisting of multiple metal layers (first work function metal layer, second work function metal layer) combined with high-k dielectric material. This composite structure replaces the single-material polysilicon gate, enabling independent optimization of gate capacitance (through high-k dielectric) and work function (through metal layers), thereby resolving the contradiction between fabrication simplicity and device performance.
Solution Approach 2:
The patent changes the material parameters of the gate structure by transitioning from polysilicon to metal/high-k composite. Specifically, it adjusts the work function through selective metal materials (e.g., tungsten for n-type, titanium nitride for p-type) and increases gate capacitance through high-k dielectric materials, thereby improving driving force while maintaining fabrication feasibility.
2Ease of manufacture
If high-k metal transistor is fabricated with conventional spacer formation, then process is straightforward, but over-etching and undercut occur causing erosion of high-k dielectric layer and bottom barrier metal
Solution Approach 1:
The patent applies a bottom barrier metal layer beneath the high-k dielectric layer before spacer formation. This preliminary protective layer prevents etching gas from directly attacking and eroding the high-k dielectric and underlying structures during spacer etching, thereby maintaining manufacturing precision while allowing straightforward spacer formation processes.
Solution Approach 2:
The bottom barrier metal layer acts as an intermediary protective layer between the etching process and the sensitive high-k dielectric layer. It absorbs or blocks the harmful effects of over-etching and undercut, preventing direct damage to the high-k dielectric and underlying structures, thus resolving the contradiction between process simplicity and etching control.
3Ease of manufacture
If uniform bottom barrier metal layer is formed across all regions, then fabrication is simple, but it cannot address different performance requirements of different device regions
Solution Approach 1:
The patent implements different bottom barrier metal layer thicknesses in different regions (first region with greater thickness, second region with lesser thickness) to match the specific performance requirements of each region. This local quality approach allows optimization of device characteristics in different areas while maintaining a relatively simple fabrication process that can accommodate thickness variations.
Solution Approach 2:
The patent divides the substrate into different regions (first region and second region) with distinct bottom barrier metal layer thicknesses. This segmentation enables independent optimization of each region's performance characteristics while using a unified fabrication approach, thereby balancing manufacturing simplicity with region-specific adaptability.
Data Source
AI summary
A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.