High-k Gate Spacer Fabrication via Pressure-Modulated Gas Treatment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional polysilicon gates in semiconductor devices face issues like boron penetration and depletion effects, leading to reduced gate capacitance and current leakage in high-k metal transistor fabrication, necessitating an improvement in the fabrication process.
Innovation Solution
A method involving a substrate with a gate structure and high-k dielectric layer, where ambient pressure is increased by injecting a low activity gas before spacer formation, followed by pressure reduction and temperature ramping to enhance surface charge neutralization and surface repair.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional polysilicon gate is used, then gate electrode can be formed, but boron penetration and depletion effect occur leading to reduced gate capacitance and increased current leakage
Solution Approach 1:
The patent changes the material parameter of the gate electrode from conventional polysilicon to metal gate materials (such as tungsten, molybdenum, or their silicides). This material substitution eliminates boron penetration and depletion effects, thereby improving gate capacitance and reducing current leakage without compromising gate electrode formation
Solution Approach 2:
The patent employs a composite structure combining metal gate electrode with high-k dielectric layer. This composite material system provides both the electrical functionality of the gate and the insulating properties needed, while avoiding the harmful effects associated with polysilicon gates
2Ease of manufacture
If furnace deposition with temperature ramp approach is used for spacer formation, then dielectric layer can be deposited, but current leakage remains unsatisfactory
Solution Approach 1:
The patent applies a preliminary surface treatment step before spacer formation where the substrate surface is treated (such as through plasma treatment or chemical modification) to improve surface quality and charge neutrality. This preliminary action prevents current leakage issues that would otherwise occur during subsequent furnace deposition and spacer formation processes
Solution Approach 2:
The patent modifies the deposition environment by using controlled atmosphere (such as nitrogen or inert gas environment) during the spacer formation process. This inert environment prevents unwanted chemical reactions and surface degradation that lead to current leakage, while still allowing the dielectric layer to be successfully deposited
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves current leakage by neutralizing surface charges and repairing exposed surfaces, resulting in enhanced device performance.
Implementation Method 1
charges generated on the surface of gate structure and substrate could be neutralized significantly by the introduction of low activity gas
Implementation Method 2
exposed surfaces of the silicon layer and high-k dielectric layer from gate structure as well as substrate could also be repaired by the introduction of low activity gas
Data Source
AI summary
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having gate structure thereon, wherein the gate structure comprises a high-k dielectric layer; increasing an ambient pressure around the gate structure to a predetermined pressure by injecting a first gas; reducing the ambient pressure to a base pressure; and forming a spacer around the gate structure.