High-k Metal Gate Layout for Transverse Tensile Stress
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Solution Overview
Problem
Current semiconductor fabrication processes for high-k metal gate transistors lack effective means to increase tensile stress in the transverse direction, which affects device performance by reducing gate capacitance and driving force.
Innovation Solution
The method involves forming shallow trench isolation (STI) in a substrate, creating trenches adjacent to the gate structure, and depositing a contact etch stop layer (CESL) into these trenches to enhance tensile stress, which is achieved by etching processes and subsequent deposition steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional polysilicon gate is used, then fabrication process is simple, but device performance deteriorates due to boron penetration and depletion effect
Solution Approach 1:
The patent changes the material parameter of the gate electrode from conventional polysilicon to high-k metal gate materials (such as HfO2, TiN, TaN), which fundamentally alters the electrical characteristics and eliminates boron penetration and depletion effects, thereby improving device performance while maintaining fabrication feasibility
Solution Approach 2:
The patent employs a composite gate structure consisting of high-k dielectric layer and metal gate electrode, combining materials with different properties to achieve both high capacitance and low resistance, resolving the performance limitations of single-material polysilicon gates
2Device complexity
If no tensile stress enhancement structure is added, then device structure remains simple, but carrier transmission speed decreases
Solution Approach 1:
The patent applies tensile stress enhancement locally by forming CESL only in specific regions (source/drain areas) rather than uniformly across the entire device, thereby improving carrier transmission speed in critical areas while minimizing overall structural complexity
Solution Approach 2:
The patent segments the stress enhancement structure into discrete CESL regions positioned at source and drain areas, allowing independent optimization of stress application without requiring complex global structural changes
3Stress or pressure
If CESL is formed in trenches adjacent to gate structure, then tensile stress increases, but fabrication process complexity increases
Solution Approach 1:
The patent performs the CESL formation step during the existing fabrication sequence at an optimized timing point, incorporating the stress enhancement structure into the standard process flow rather than adding a separate complex fabrication stage
Solution Approach 2:
The CESL formation process serves multiple functions simultaneously: it creates the etch stop layer for subsequent processing, introduces tensile stress to enhance carrier mobility, and defines regional stress patterns, thereby reducing the need for separate dedicated process steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases tensile stress in the transverse direction, thereby improving carrier transmission speed and device performance for both NMOS and PMOS transistors.
Implementation Method 1
performing an etching process to remove part of the STI for forming a first trench adjacent to one side of the gate structure and a second trench adjacent to another side of the gate structure
Implementation Method 2
forming a contact etch stop layer (CESL) on the gate structure and into the first trench and the second trench
Data Source
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AI summary
A method for fabricating semiconductor device includes the steps of first forming a shallow trench isolation (STI) in a substrate, forming a gate structure on the STI and the substrate, forming a patterned mask on the STI and the gate structure, performing an etching process to remove part of the STI for forming a first trench adjacent to one side of the gate structure and a second trench adjacent to another side of the gate structure, and then forming a contact etch stop layer (CESL) on the gate structure and into the first trench and the second trench.