Triple High-k Gate Stack for CMOS Vt Tuning and Reliability
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Solution Overview
Problem
Existing methods for tuning the threshold voltage of the gate stack are challenging as devices continue to scale down to multi-gate devices, and there is not much room for tuning their Vt's using different work function metals.
Innovation Solution
The present disclosure utilizes a triple layer high-k solution for tuning Vt's in CMOS devices, employing a common thin layer of work function metal over a triple layer high-k gate dielectric stack, which includes a dipole material in lower layers to adjust Vt by about 50 mV to about 300 mV, and an upper layer free from dipole material to maintain reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If devices are scaled down to multi-gate devices, then production efficiency and cost are improved, but Vt tuning capability deteriorates
Solution Approach 1:
The gate dielectric is segmented into multiple layers with different functions: a first gate dielectric layer providing baseline insulation, and a second gate dielectric layer containing dipole materials for Vt tuning. This segmentation allows independent optimization of each layer's properties to achieve both scaling and tuning capabilities.
Solution Approach 2:
The second gate dielectric layer is selectively formed only in regions where Vt tuning is required, while the first gate dielectric layer provides universal coverage. This local quality approach enables Vt tuning capability to be introduced precisely where needed without affecting the entire device uniformly.
2Adaptability or versatility
If dipole material is added to tune Vt, then Vt adjustment range is improved, but device reliability deteriorates
Solution Approach 1:
The gate dielectric is divided into two distinct layers: the first layer provides stable, reliable insulation without dipole materials, while the second layer contains dipole materials for Vt tuning. This segmentation isolates the reliability-critical first layer from the tuning-function second layer, allowing Vt adjustment without compromising overall device reliability.
Solution Approach 2:
The first gate dielectric layer acts as an intermediary barrier between the channel and the dipole-containing second layer. This intermediary structure prevents direct interaction between the channel and potentially unstable dipole materials, thereby maintaining device reliability while still enabling Vt tuning through the second layer.
3Manufacturing precision
If work function metal thickness is increased for Vt tuning, then Vt control is improved, but manufacturing complexity increases
Solution Approach 1:
Instead of changing the thickness or composition of the work function metal layer, the invention changes the parameters of the gate dielectric layers—specifically, introducing a second layer with dipole materials. This parameter change in the dielectric structure provides Vt tuning capability without increasing metal layer complexity or requiring additional metal deposition processes.
Solution Approach 2:
The invention replaces the mechanical approach of thickening the work function metal layer with a chemical/electrical approach using dipole materials in the gate dielectric. The dipole materials provide Vt tuning through their electrical properties rather than through physical thickness changes, thereby avoiding increased manufacturing complexity associated with thicker metal layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The triple layer high-k gate dielectric stack allows for flexible tuning of both NMOS and PMOS transistors, reducing power consumption and boosting device performance in small-sized FinFET and GAA devices.
Implementation Method 1
employing a common thin layer of work function metal over a triple layer high-k gate dielectric stack, which includes a dipole material in lower layers to adjust Vt by about 50 mV to about 300 mV
Data Source
AI summary
A method includes providing first and second channel layers in NMOS and PMOS regions respectively of a substrate; depositing a first layer comprising hafnium oxide over the first and second channel layers; forming a first dipole pattern over the second channel layer and not over the first channel layer; driving a first metal from the first dipole pattern into the first layer by annealing; removing the first dipole pattern; depositing a second layer comprising hafnium oxide over the first layer and over the first and second channel layers; forming a second dipole pattern over the second layer and the first channel layer and not over the second channel layer; driving a second metal from the second dipole pattern into the second layer by annealing; removing the second dipole pattern; and depositing a third layer comprising hafnium oxide over the second layer and over the first and the second channel layers.