High-k Interface Layer for CMOS Transistor EOT Reduction
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Solution Overview
Problem
In high-k gate dielectric/metal gate semiconductor devices, the continuous thinning of the interface layer to reduce equivalent oxide thickness (EOT) leads to atom diffusion from the high-k gate dielectric into the channel region during high-temperature treatment, degrading carrier mobility and causing interface state and roughness issues.
Innovation Solution
A method involving the formation of multi-component high-k interface layers containing substrate elements through rapid annealing of ultra-thin high-k dielectric materials, followed by the deposition of high-k gate dielectric layers with higher dielectric constants, which reduces EOT and prevents atom diffusion, thereby enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the interface layer is continuously thinned to reduce equivalent oxide thickness (EOT), then EOT is reduced, but atom diffusion from the high-k gate dielectric into the channel region occurs during high-temperature treatment, degrading carrier mobility
Solution Approach 1:
The patent introduces an ultra-thin interface layer (0.1-1 nm) as an intermediary between the high-k gate dielectric and the semiconductor substrate. This interface layer acts as a diffusion barrier that prevents atom diffusion during high-temperature treatment while maintaining the reduced EOT. The interface layer is formed by depositing high-k dielectric material and performing rapid annealing to create a controlled transition region that mediates between the dielectric and substrate.
Solution Approach 2:
The patent changes the physical and chemical parameters of the interface layer by controlling its thickness (0.1-1 nm) and composition through rapid annealing. The annealing process transforms the deposited high-k material into an ultra-thin interface layer with specific properties that balance EOT reduction and diffusion prevention. The rapid annealing parameters (temperature, time, atmosphere) are optimized to achieve the desired interface characteristics.
2Manufacturing precision
If the interface layer is thinned to reduce EOT, then EOT is reduced, but interface state and roughness issues occur
Solution Approach 1:
The ultra-thin interface layer serves as a mediator that improves interface quality by providing a controlled transition region between the high-k dielectric and substrate. This intermediary layer reduces interface states and roughness by creating a gradual transition rather than a sharp interface, thereby maintaining good electrical properties while enabling EOT reduction.
Solution Approach 2:
The rapid annealing process changes the physical and chemical parameters of the interface region, reducing interface states and improving uniformity. The annealing transforms the as-deposited material into a more stable interface structure with reduced defects and improved morphology, thereby enhancing interface quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces EOT, prevents degradation of carrier mobility, and alleviates interface state and roughness issues, resulting in improved overall device performance by forming optimized high-k interface layers and high-k gate dielectric layers with higher dielectric constants.
Implementation Method 1
the optimized high-k interface layer containing elements of the substrate has a higher density of atoms and more advantageously blocks the diffusion of oxygen
Implementation Method 2
by using rapid annealing, and forming a high-k gate dielectric layer with a higher dielectric constant thereon
Data Source
AI summary
A semiconductor device is provided. A multi-component high-k interface layer containing elements of the substrate is formed from an ultra-thin high-k dielectric material in a single-layer structure of atoms by rapid annealing in the manufacturing of a CMOS transistor by the replacement gate process, and a high-k gate dielectric layer with a higher dielectric constant and a metal gate layer are formed thereon. The EOT of the device is effectively decreased, and the diffusion of atoms in the high-k gate dielectric layer from an upper level thereof is effectively prevented by the optimized high-k interface layer at high-temperature treatment.