High-k Gate Dielectric Tuning by Selective Metal Diffusion
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Solution Overview
Problem
The traditional semiconductor industry faces challenges in reducing the size of semiconductor devices while maintaining excellent characteristics, as the silicon-dioxide gate dielectric layer approaches its physical limit, leading to increased leakage current and poor device performance, and the high-k/metal-gate (HKMG) process is complex and costly due to the need for multiple photoetching mask layers.
Innovation Solution
A manufacturing method for a semiconductor device involving a substrate with high-k gate dielectric layers, a barrier layer structure, and a covering layer film with a first metal element, where the annealing process diffuses the metal element into the high-k gate dielectric layer at one device region while preventing diffusion at the other, allowing for the formation of gate dielectric layers with different dielectric constants using fewer process steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate oxide layer is made thinner to inhibit short channel effect, then device characteristics are improved, but direct tunneling effect increases causing leakage current
Solution Approach 1:
The patent changes the dielectric constant parameter of the gate dielectric layer from traditional silicon dioxide (k=3.9) to high-k materials (k>25), allowing the physical thickness to be increased while maintaining equivalent electrical thickness, thus reducing tunneling current while preserving gate control
2Object-generated harmful factors
If high-k/metal-gate is used to replace poly/SiO2 gate stack, then leakage current is reduced, but manufacturing process becomes complicated and cost increases
Solution Approach 1:
The patent merges the gate dielectric layer formation and gate electrode formation into a unified process sequence, where the high-k dielectric layer serves as both the gate dielectric and the base for the metal gate, eliminating separate photomask steps for gate dielectric and gate electrode patterning
Solution Approach 2:
The high-k gate dielectric layer performs multiple functions: it serves as the gate dielectric layer, provides a diffusion barrier for metal elements, and acts as the foundation for the metal gate electrode, reducing the need for separate functional layers
3Adaptability or versatility
If multiple photoetching mask layers are used for gate-first HKMG transistor, then different gate dielectric layers are formed, but production cycle and cost increase
Solution Approach 1:
The patent forms the high-k gate dielectric layer uniformly across all device regions before any photomask patterning steps, allowing subsequent selective removal or modification in different regions without requiring separate dielectric formation steps for each region
Solution Approach 2:
The patent applies selective photomask patterning to the pre-formed high-k gate dielectric layer, removing or modifying it in specific regions (such as PMOS regions) while retaining it in other regions (such as NMOS regions), creating different gate structures without multiple dielectric formation steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces the production cycle and cost by eliminating the need for multiple photoetching mask layers, enabling the formation of high-k gate dielectric layers with different dielectric constants for PMOS and NMOS regions, thereby improving device performance and efficiency.
Implementation Method 1
performing an annealing process, the first metal element being diffused towards the high-k gate dielectric layer film at the first device region
Implementation Method 2
the barrier layer structure preventing the first metal element from being diffused towards the high-k gate dielectric layer film at the second device region
Data Source
AI summary
The present application relates to a semiconductor device and a manufacturing method thereof. The method includes: obtaining a substrate, a first device region, a second device region and a high-k gate dielectric layer film being formed on the substrate; forming, on the substrate, a barrier layer structure covering the high-k gate dielectric layer film at the second device region; forming a covering layer film including a first metal element on the substrate; and diffusing the first metal element in the covering layer film towards the high-k gate dielectric layer film at the first device region using an annealing process, the barrier layer structure preventing the first metal element from being diffused towards the high-k gate dielectric layer film at the second device region; wherein the first device region and the second device region have opposite conduction types.