High-K Metal Gate Stack Capping Layer for Leakage Reduction
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Solution Overview
Problem
Conventional gate replacement processes in semiconductor IC manufacturing face challenges such as gap fill issues and higher than desirable gate leakage, especially as technology nodes continue to decrease, necessitating an improved method for fabricating IC devices with metal gate electrodes.
Innovation Solution
A method involving the formation of a multi-layer capping layer including titanium nitride and tantalum nitride layers before forming a dummy gate structure, which allows for complete filling of openings with metal gates and acts as an etch stop layer to prevent damage to high-k dielectric layers during the gate replacement process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate replacement process is used, then the process can be implemented with standard fabrication steps, but gap fill issues occur and gate leakage increases
Solution Approach 1:
The patent segments the gate stack formation into distinct stages: forming a dummy gate structure first, then selectively removing it to create openings, and finally filling with metal gate electrode. This segmentation allows each step to be optimized independently, solving the gap fill issue by ensuring complete opening formation before metal deposition, and reducing gate leakage through controlled interface formation between the metal gate electrode and high-k dielectric layer.
Solution Approach 2:
The patent performs preliminary actions by forming a dummy gate structure before defining the final gate pattern, and by preparing the high-k dielectric layer and capping layers before opening formation. This preliminary structuring enables subsequent etching and filling processes to proceed with better control, eliminating gap fill voids and ensuring proper metal gate electrode placement to reduce leakage current.
2Productivity
If the gate length and spacing between devices decreases, then device density increases, but gap fill issues and gate leakage are exacerbated
Solution Approach 1:
The patent applies local quality by forming different capping layers with specific properties at different locations within the gate stack. The first capping layer provides protection during processing, while the second capping layer is specifically engineered to interface with the metal gate electrode, providing local optimization of the gate-dielectric interface to reduce leakage current in high-density devices with reduced gate length and spacing.
3Manufacturing precision
If a multi-layer capping layer is formed before dummy gate, then gap filling is improved and leakage is reduced, but process complexity increases
Solution Approach 1:
The patent merges the formation of multiple capping layers into a coordinated sequence before dummy gate formation, where the first and second capping layers are deposited in succession and then patterned together with the dummy gate structure. This merging approach ensures that all protective and functional layers are in place before opening formation, enabling complete gap fill without requiring separate processing steps for each layer, thus managing process complexity while achieving improved manufacturing precision.
Data Source
AI summary
A method for fabricating an integrated circuit device is disclosed. An exemplary method includes providing a substrate; forming a high-k dielectric layer over the substrate; forming a first capping layer over the high-k dielectric layer; forming a second capping layer over the first capping layer; forming a dummy gate layer over the second capping layer; performing a patterning process to form a gate stack including the high-k dielectric layer, first and second capping layers, and dummy gate layer; removing the dummy gate layer from the gate stack, thereby forming an opening that exposes the second capping layer; and filling the opening with a first metal layer over the exposed second capping layer and a second metal layer over the first metal layer, wherein the first metal layer is different from the second metal layer and has a work function suitable to the semiconductor device.