High-K Metal Gate Stack Capping Layer for Vt Control
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Solution Overview
Problem
Conventional methods for integrating transistors with different threshold voltage requirements in integrated circuits face challenges due to dopant fluctuations, leading to variability in device performance, especially as feature sizes are scaled.
Innovation Solution
The use of high-K/metal gate stacks with a capping layer and crystalline silicon-germanium (cSiGe) to selectively alter the threshold voltage of transistors, allowing for consistent and accurate differentiation between SRAM and logic transistors without the need for extensive doping adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If doping is used to adjust threshold voltage of transistors, then threshold voltage differentiation between SRAM and logic transistors is achieved, but dopant fluctuations cause variability in device performance
Solution Approach 1:
The patent changes the physical parameter of the gate stack by introducing a capping layer with specific material properties (e.g., work function, thickness) to adjust the threshold voltage. This replaces the doping-based parameter adjustment with a gate stack parameter adjustment, avoiding dopant fluctuations while achieving the required threshold voltage differentiation between SRAM and logic transistors
Solution Approach 2:
The patent employs a composite gate stack structure consisting of multiple layers including a high-K dielectric layer and a metal capping layer. This composite structure enables precise control of threshold voltage through the combination of different materials with complementary properties, eliminating reliance on doping while maintaining device performance consistency
2Productivity
If feature sizes are scaled down, then device density and integration are improved, but dopant fluctuations and device variability become more pronounced
Solution Approach 1:
The patent changes the threshold voltage control mechanism from doping concentration to gate stack physical parameters (capping layer thickness, material composition). This parameter change enables precise control even at scaled feature sizes where dopant fluctuations would otherwise dominate and cause excessive device variability
Solution Approach 2:
The patent substitutes the chemical doping mechanism with a physical gate stack structure mechanism. The capping layer's physical properties (work function, thickness) directly control the electric field at the interface, replacing the need for dopant introduction and enabling better control at scaled dimensions where mechanical/physical effects dominate over chemical diffusion
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes variability and enhances the accuracy of threshold voltage adjustments, reducing the impact of dopant fluctuations and improving device performance by providing a consistent and scalable solution for integrating transistors with different voltage requirements.
Implementation Method 1
Each of the logic nFET, logic pFET, SRAM nFET and SRAM pFET comprises a gate stack having a metal layer over a high-K layer
Implementation Method 2
the capping layer is further configured to shift a Vt of the logic nFET relative to a Vt of one or more of the logic pFET, SRAM nFET and SRAM pFET
Data Source
AI summary
Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.