High-K Metal Gate CMOS Integration via Protective Intermediary Layers
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Solution Overview
Problem
The integration of high-k/metal gates in CMOS process flows faces challenges due to material incompatibility and complex processes, particularly in damaging high-k dielectric layers during etching and thermal processes, and the complexity of forming dual metal gates as device features shrink.
Innovation Solution
A method involving a hybrid gate process where metal gates for NMOS and PMOS devices are formed in a specific sequence, with partial removal of metal layers before poly etch back, and using protective metal layers to prevent high-k dielectric damage, allowing for simpler N/P patterning and reduced risk of high-k dielectric damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-k dielectric layer is used to replace gate oxide, then device performance is improved, but the dielectric layer becomes susceptible to damage during etching and thermal processes
Solution Approach 1:
A protective metal layer is introduced as an intermediary between the high-k dielectric layer and the etching/thermal processes. This protective layer shields the high-k dielectric from direct exposure to harmful etchants and thermal stress, preventing damage while allowing the high-k dielectric to maintain its performance benefits.
Solution Approach 2:
The protective metal layer is formed prior to subsequent etching and thermal processes. This preliminary protective action ensures that the high-k dielectric layer is already shielded before any potentially damaging operations are performed, preventing damage proactively rather than remedially.
2Reliability
If dual metal gates are formed for NMOS and PMOS devices, then device performance is enhanced, but process complexity increases significantly
Solution Approach 1:
The formation of dual metal gates for NMOS and PMOS devices is merged into a single integrated process flow. By combining the metal gate formation steps and using common process parameters where possible, the complexity of forming separate metal gates is reduced while still achieving the performance benefits of dual metal gates.
Solution Approach 2:
Different metal layers are selectively applied to different device regions (NMOS vs PMOS) based on local requirements. The protective metal layer and subsequent metal gate materials are patterned and deposited with region-specific properties, allowing optimized performance for each transistor type while managing overall process complexity.
3Object-affected harmful factors
If metal layers are removed before poly etch back, then high-k dielectric damage is reduced, but additional process steps are required
Solution Approach 1:
The protective metal layer serves as a sacrificial intermediary that is removed before the poly etch back step. This intermediary layer absorbs the damage that would otherwise affect the high-k dielectric during poly removal, and its temporary presence is justified by the protection it provides.
Solution Approach 2:
The removal of the protective metal layer, which initially seems to add complexity, actually converts a potential harm (exposure of high-k dielectric to poly etch back damage) into a benefit (protected high-k dielectric). The temporary addition of this step prevents greater damage that would occur without it.
Data Source
AI summary
A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first region and a second region, forming a first dielectric layer over the semiconductor substrate, forming a first metal layer over the first dielectric layer, the first metal layer having a first work function, removing at least a portion of the first metal layer in the second region, and thereafter, forming a semiconductor layer over the first metal layer in the first region and over the at least partially removed first metal layer in the second region. The method further includes removing the semiconductor layer and forming a second metal layer on the first metal layer in the first region and on the at least partially removed first metal layer in the second region, the second metal layer having a second work function that is different than the first work function.