Tuning High-K Metal Gate Work Functions via Reflowed TiAl
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Solution Overview
Problem
The scaling down of semiconductor integrated circuits has led to increased complexity and power dissipation, with existing methods using capping layers to tune work functions for metal gates affecting carrier mobility and device performance.
Innovation Solution
A method involving the formation of trenches in a semiconductor substrate, where metal layers are deposited and reflowed to form a TiAl layer, allowing for the tuning of work functions without the need for capping layers, thereby improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If capping layers are used to tune the work function of metal gates, then the work function can be adjusted for NMOS and PMOS devices, but carrier mobility decreases and device performance is adversely affected
Solution Approach 1:
The gate structure is segmented into multiple functional layers: a metal gate electrode layer for work function tuning, a barrier layer adjacent to the high-k dielectric, and an interfacial layer at the semiconductor interface. This segmentation allows the metal gate electrode to be tuned for work function without requiring capping layers, thereby preserving carrier mobility while achieving the desired work function adjustment.
2Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency increases and costs decrease, but power dissipation increases
Solution Approach 1:
The patent employs a high-k dielectric material with increased dielectric constant compared to traditional silicon oxide. This parameter change allows for thinner effective oxide equivalents while maintaining or increasing the physical thickness of the gate dielectric layer, thereby reducing gate leakage current and power dissipation while enabling continued scaling for higher functional density.
3Reliability
If a high-k gate dielectric and metal gate electrode are used to improve device performance, then device performance improves, but the complexity of processing and manufacturing increases
Solution Approach 1:
The patent forms an interfacial layer between the high-k dielectric and the semiconductor substrate before depositing the metal gate electrode. This preliminary action prepares the interface to prevent degradation of the high-k dielectric and ensures proper electrical characteristics, simplifying subsequent processing steps and reducing manufacturing complexity while maintaining improved device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient tuning of work functions for NMOS and PMOS devices, enhancing carrier mobility and device performance while being cost-effective and compatible with existing CMOS process flows.
Implementation Method 1
A thermal process is used to reflow the second metal layer and the third metal layer
Data Source
AI summary
A method of fabricating a semiconductor device includes forming a first trench and a second trench on a semiconductor substrate and forming a first metal layer in the first and second trenches. The first metal layer is then removed, at least partially, from within the first trench but not the second trench. A second metal layer and a third metal layer are formed in the first and second trenches. A thermal process is used to reflow the second metal layer and the third metal layer.