High-k Metal Gate Stack Fabrication for CMOS Integration
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Solution Overview
Problem
The integration of high-k and metal gate stacks in semiconductor integrated circuits is challenging due to complexity in forming various types of field-effect transistors on a single IC chip, requiring a flexible and efficient fabrication process.
Innovation Solution
A method involving a semiconductor substrate with doped regions and isolation features, where different gate stacks are formed by depositing and patterning high-k dielectric layers, capping layers, work function metal layers, and polysilicon layers, allowing for the integration of multiple types of field-effect transistors and resistors with varying work function configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional fabrication processes are used for integrating high-k and metal gate stacks, then manufacturing simplicity is maintained, but flexibility to fabricate various HK/MG structures for different FET types is insufficient
Solution Approach 1:
The gate stack fabrication process is segmented into distinct sequential steps: forming interfacial layers, depositing high-k dielectric layers, depositing first capping layers, patterning, depositing second capping layers, and selective removal. This segmentation allows independent optimization of each step and enables flexible combination for different FET types without requiring complete process redesign.
Solution Approach 2:
The patent employs universal layer structures (interfacial layer, high-k dielectric layer, capping layers) that can be used across multiple FET types (p-type, n-type, input/output, high-resistor). The same basic stack structure serves multiple functions by varying the thickness, material composition, and selective removal of layers, providing a multi-functional platform for diverse device requirements.
2Reliability
If multiple different gate stack types are formed for different FET regions, then device performance is optimized, but fabrication process complexity increases
Solution Approach 1:
The patent implements local quality by applying selective removal processes to specific regions. First capping layers are selectively removed in p-type FET core regions and input/output pFET regions, while second capping layers are selectively removed in n-type FET core regions and input/output nFET regions. This localized differentiation achieves optimal device performance without requiring completely separate fabrication lines.
Solution Approach 2:
The interfacial layers are formed preliminarily across all regions before any high-k dielectric or capping layer deposition. This preliminary action establishes a uniform foundation that simplifies subsequent processing steps and ensures consistent device characteristics across different FET types, reducing overall manufacturing complexity.
3Productivity
If various HK/MG structures are integrated onto a single IC chip, then functional density is increased, but integration challenges arise
Solution Approach 1:
The patent merges the fabrication processes for different FET types into a single integrated process flow. Multiple gate stack variations are created within one continuous manufacturing sequence by combining common deposition steps with selective removal steps, enabling high functional density on a single chip while managing integration complexity through process consolidation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables flexible and efficient fabrication of various gate stacks, facilitating the integration of CMOS devices while maintaining reasonable threshold voltages for both NMOS and PMOS devices, and allows for simultaneous formation of multiple gate stacks, enhancing production efficiency.
Implementation Method 1
depositing a high-k dielectric layer on the interfacial layer
Implementation Method 2
depositing a capping layer of a first material on the high-k dielectric layer, depositing a capping layer of a second material on the high-k dielectric layer and on the capping layer of the first material
Data Source
AI summary
A method for fabricating a semiconductor device includes providing a semiconductor substrate having regions for an n-type field-effect transistor (nFET) core, an input/output nFET (nFET IO), a p-type field-effect transistor (pFET) core, an input/output pFET (pFET IO), and a high-resistor, forming an oxide layer on the IO regions of the substrate, forming an interfacial layer on the substrate and the oxide layer, depositing a high-k (HK) dielectric layer on the interfacial layer, depositing a first capping layer of a first material on the HK dielectric layer, depositing a second capping layer of a second material on the HK dielectric layer and on the first capping layer, depositing a work function (WF) metal layer on the second capping layer, depositing a polysilicon layer on the WF metal layer, and forming gate stacks on the regions of the substrate.