High-k Metal Gate Stack Integrity via STI Formation Sequence
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Solution Overview
Problem
The fabrication of advanced integrated circuits using CMOS technology faces challenges with gate failures and process non-uniformities due to insufficient encapsulation of sensitive high-k metal gate electrode structures, particularly in the transition areas between active and isolation regions, leading to increased leakage currents and reduced transistor performance.
Innovation Solution
Forming critical materials of high-k metal gate electrode structures before creating isolation regions, ensuring that these materials are positioned only above active regions, thereby reducing surface topography and preventing exposure of gate materials above isolation regions, which enhances process uniformity and transistor characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If isolation regions are formed before gate electrode structures, then the fabrication process follows conventional sequencing, but gate failures and process non-uniformities occur due to insufficient encapsulation of sensitive high-k metal gate materials in transition areas
Solution Approach 1:
The patent applies preliminary action by forming the high-k metal gate electrode structures before creating the isolation regions. This sequence ensures that the sensitive gate materials are already in place and can be properly encapsulated by the isolation regions, preventing exposure and degradation during subsequent processing steps. The gate electrode structures are formed with precise positioning over active regions only, ensuring uniformity and reliability.
Solution Approach 2:
The patent inverts the conventional fabrication sequence by reversing the order of forming isolation regions and gate electrode structures. Instead of forming isolation regions first and then gate structures, the patent forms gate structures first and then isolation regions. This inversion resolves the encapsulation issue by ensuring that isolation regions are created after the sensitive gate materials are already positioned, thereby protecting them from exposure and process non-uniformities.
2Reliability
If high-k metal gate materials are positioned over isolation regions, then complete gate coverage is achieved, but mechanical stability is compromised and gate failures increase due to material exposure in transition areas
Solution Approach 1:
The patent applies local quality by ensuring that high-k metal gate electrode structures are positioned only over active regions and not over isolation regions. This localized positioning provides precise control over where the sensitive materials are placed, ensuring they are protected and encapsulated where needed (over active regions) while avoiding mechanical instability and exposure issues in transition areas. The gate electrode structures are formed with specific lateral dimensions that confine them to active regions only.
3Manufacturing precision
If conventional fabrication sequencing is used, then process flow is straightforward, but surface topography variations and process non-uniformities occur due to pronounced topography in isolation regions
Solution Approach 1:
The patent applies preliminary action by forming the gate electrode structures before creating isolation regions. This sequence allows the gate materials to be deposited on a relatively flat surface before the isolation regions are formed, avoiding the pronounced topography variations that would occur if gate materials were deposited over pre-formed isolation regions. The result is more uniform surface topography and reduced process non-uniformities.
Data Source
AI summary
When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage, superior process robustness, reduced yield loss and an enhanced degree of flexibility in designing the overall process flow may be accomplished by forming and patterning the sensitive gate materials prior to forming isolation regions.