High-K Metal Gate Transistor Topography Control via Selective Etch Masking
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Solution Overview
Problem
The manufacturing sequence for forming high-k metal gate electrode structures in integrated circuits introduces asymmetry in surface topography between P-channel and N-channel transistors, leading to variability in transistor characteristics due to uneven material loss during etch and deposition processes, which affects the symmetry of active and isolation regions.
Innovation Solution
A process sequence is implemented to achieve symmetry in active and isolation regions by controlling material loss during reactive etch chemistries, using etch masks to uniformly expose regions and forming threshold adjusting semiconductor alloys, thereby improving surface topography and reducing non-uniformities in gate electrode structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a mask layer is selectively removed from only one active region to form threshold adjusting semiconductor alloy, then the transistor threshold voltage can be adjusted, but asymmetry in surface topography is introduced between P-channel and N-channel transistors
Solution Approach 1:
The patent intentionally introduces asymmetry in the mask layer configuration - a first mask layer is formed on the first active region while a second mask layer is formed on the second active region. This asymmetric masking allows selective removal of mask material from only one active region, enabling threshold voltage adjustment in specific transistors (e.g., P-channel vs N-channel) while maintaining controlled symmetry in the overall fabrication process.
Solution Approach 2:
The mask layers are formed preliminarily before the threshold adjusting semiconductor alloy deposition. This preliminary masking action defines which regions will receive the alloy and controls the material loss in isolation regions during subsequent etch processes, thereby preparing the surface topography in advance to minimize asymmetry issues.
2Adaptability or versatility
If threshold adjusting semiconductor alloy is formed selectively in one active region, then transistor characteristics can be optimized, but variability in transistor characteristics increases due to topography asymmetry
Solution Approach 1:
The patent intentionally creates asymmetric threshold adjusting - the first threshold adjusting semiconductor alloy is formed in the first active region while the second is formed in the second active region. This allows optimization of transistor characteristics for different transistor types (e.g., P-channel requiring different threshold voltage than N-channel) while the controlled mask layer removal process maintains sufficient topography symmetry to minimize variability.
Solution Approach 2:
The patent changes material parameters by forming different threshold adjusting semiconductor alloys in different active regions. The first alloy composition and the second alloy composition can be different, allowing optimization of transistor characteristics for each transistor type while maintaining process control through symmetric mask layer formation and removal.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced transistor variability by ensuring uniformity in surface topography and material composition, leading to more consistent and reliable high-k metal gate electrode structures with improved critical dimensions and confinement.
Implementation Method 1
forming a layer of a semiconductor alloy on the first active region and using the mask layer on the second active region as a growth mask
Implementation Method 2
forming a first etch mask so as to cover the second active region and expose the first active region
Data Source
AI summary
In a manufacturing strategy for providing high-k metal gate electrode structures in an early manufacturing stage, process-related non-uniformities during and after the patterning of the gate electrode structures may be reduced by providing a superior surface topography. To this end, the material loss in the isolation region may generally be reduced and a more symmetrical exposure to reactive etch atmospheres during the subsequent removal of the growth mask may be accomplished by providing an additional etch mask when removing the growth mask from the active regions of N-channel transistors, after the growth of the threshold adjusting semiconductor material on the active regions of the P-channel transistors.