High-K Metal Gate Transistor Stability via Wet Cleaning
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Solution Overview
Problem
The fabrication of advanced integrated circuits using high-k gate dielectric materials and strain-inducing semiconductor alloys faces challenges in maintaining uniform transistor characteristics and reducing threshold voltage variability, particularly as transistor dimensions are scaled down, leading to increased leakage current and variations in transistor performance.
Innovation Solution
A superior cleaning regime is implemented after forming cavities in the active region, involving a first wet cleaning process to remove contaminants and condition surface areas without modifying sensitive materials, followed by a second wet cleaning process before epitaxial growth, using de-ionized water and specific cleaning agents like sulfuric acid, ozone, hydrogen peroxide, and hydrogen fluoride to prevent interaction with high-k dielectric materials and adjust semiconductor alloy properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a thin silicon dioxide gate dielectric layer is used to maintain capacitive coupling in scaled transistors, then the transistor switching speed improves, but the leakage current increases exponentially
Solution Approach 1:
The patent transitions from silicon dioxide to high-k dielectric materials, fundamentally changing the material parameter (permittivity) to achieve the desired capacitive coupling without the harmful leakage effects of ultra-thin oxide layers
Solution Approach 2:
The gate dielectric structure employs composite material stacks combining high-k dielectric layers with other functional layers, enabling simultaneous optimization of capacitance, leakage current, and interface characteristics
2Object-generated harmful factors
If high-k gate dielectric materials are used to reduce leakage current, then the leakage current decreases, but the transistor characteristics become non-uniform and threshold voltage varies
Solution Approach 1:
The patent implements locally optimized gate dielectric structures with different material compositions and thicknesses in different regions, allowing tailoring of electrical characteristics to specific device requirements while maintaining overall uniformity
Solution Approach 2:
The patent applies preliminary surface treatment and interface preparation steps before depositing high-k dielectric materials, ensuring consistent interface quality and reducing variability in transistor characteristics
3Productivity
If transistor dimensions are scaled down to increase integration density, then the number of circuit elements increases, but the leakage current increases and performance varies
Solution Approach 1:
The patent changes the gate dielectric material parameter from low-k silicon dioxide to high-k materials, enabling sufficient capacitance at thicker equivalent oxide thicknesses, which reduces leakage in scaled devices
Solution Approach 2:
The patent uses composite gate dielectric structures that combine high-k materials with other materials to achieve both high capacitance and low leakage, enabling continued scaling with controlled performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the dependence of threshold voltages on transistor width, enhancing the uniformity of transistor characteristics and reducing yield loss by preserving the integrity of sensitive gate materials and semiconductor alloys, thereby improving the performance and reliability of transistors.
Implementation Method 1
performing a first wet cleaning process so as to clean a rear side of the substrate of the semiconductor device while rinsing the active region formed in a front side of the substrate
Implementation Method 2
cleaning agents like sulfuric acid, ozone, hydrogen peroxide, and hydrogen fluoride
Implementation Method 3
cleaning agents like sulfuric acid, ozone, hydrogen peroxide, and hydrogen fluoride
Implementation Method 4
a semiconductor alloy is formed in the cavity by performing the epitaxial growth process
Data Source
AI summary
When forming sophisticated transistors on the basis of a high-k metal gate electrode structure and a strain-inducing semiconductor alloy, a superior wet cleaning process strategy is applied after forming cavities in order to reduce undue modification of sensitive gate materials, such as high-k dielectric materials, metal-containing electrode materials and the like, and modification of a threshold voltage adjusting semiconductor alloy. Thus, the pronounced dependence of the threshold voltage of transistors of different width may be significantly reduced compared to conventional strategies.