High-K Metal Gate Transistors With Embedded Strain Inducing Alloys
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Solution Overview
Problem
The fabrication of advanced integrated circuits using CMOS technology faces challenges in achieving optimal transistor performance due to issues like short channel behavior, high leakage current, and complexity in forming high-k metal gate stacks, particularly in integrating strain-inducing semiconductor materials with replacement gate approaches.
Innovation Solution
The integration of strain-inducing semiconductor materials in active regions of transistors using selective epitaxial growth techniques, allowing for the formation of cavities and regrowth of semiconductor materials to achieve desired strain components and electronic characteristics, while also forming high-k metal gate electrode structures, thereby simplifying the process flow and enhancing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If strain-inducing semiconductor materials are integrated using conventional approaches, then transistor performance can be improved, but process complexity increases significantly
Solution Approach 1:
The patent combines the formation of strain-inducing semiconductor materials with the high-k metal gate electrode structure fabrication into a unified process flow. The selective epitaxial growth of strained semiconductor regions is performed in coordination with gate dielectric deposition and metal gate formation, eliminating separate processing steps and reducing overall process complexity while maintaining performance benefits
Solution Approach 2:
The patent performs preliminary formation of strain-inducing semiconductor materials through selective epitaxial growth before completing the gate electrode structure fabrication. This preliminary action allows the strained regions to be established early in the process, enabling subsequent gate materials to be deposited conformally on the pre-formed strained structures, thereby simplifying later processing steps
2Productivity
If replacement gate approaches are used to simplify high-k metal gate stack formation, then manufacturing efficiency improves, but precise strain alignment becomes difficult to achieve
Solution Approach 1:
The patent applies selective epitaxial growth to create localized strain-inducing semiconductor regions with specific material compositions and crystal orientations in precise locations within the transistor structure. This local quality approach ensures that strain is induced only where needed, with precise alignment to the channel region, while maintaining the simplicity of replacement gate fabrication processes
Solution Approach 2:
The patent uses the high-k gate dielectric material as an intermediary layer that is deposited conformally on the pre-formed strain-inducing semiconductor structures. This intermediary deposition process automatically aligns the gate electrode with the strained regions below, achieving precise strain alignment without requiring complex additional patterning steps
3Ease of manufacture
If conventional gate dielectric thicknesses are used, then manufacturing is simpler, but leakage currents increase due to direct tunneling
Solution Approach 1:
The patent changes the dielectric parameter by transitioning from conventional silicon dioxide gate dielectrics to high-k metal oxide materials with significantly higher dielectric constants. This parameter change allows the gate dielectric layer to be made physically thicker, reducing direct tunneling leakage currents by several orders of magnitude, while maintaining the same or improved capacitive coupling and transistor switching performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved transistor performance and manufacturing efficiency by providing precise strain alignment and dopant incorporation, reducing process complexity and leakage currents, and enabling superior capacitive coupling without the need for complex patterning sequences.
Implementation Method 1
forming one or more cavities in the active region of the transistor upon removing a placeholder material of a gate electrode structure based on a replacement gate approach, wherein the cavities are formed on the basis of gate openings obtained during a replacement gate approach, and forming a semiconductor material by selective epitaxial growth techniques in the cavities
Data Source
AI summary
In sophisticated semiconductor devices, replacement gate approaches may be applied in combination with a process strategy for implementing a strain-inducing semiconductor material, wherein superior proximity of the strain-inducing semiconductor material and/or superior robustness of the replacement gate approach may be achieved by forming the initial gate electrode structures with superior uniformity and providing at least one cavity for implementing the strained channel regions in a very advanced manufacturing stage, i.e., after completing the basic transistor configuration.