Vertical High-K MIM Capacitor in Interconnect Layers
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Solution Overview
Problem
As semiconductor devices continue to integrate more components into smaller areas, metal-insulator-metal (MIM) capacitors face challenges in achieving higher capacitance while maintaining effective charge storage and electrical connectivity within the constraints of reduced feature sizes.
Innovation Solution
The fabrication of a vertical MIM capacitor with a high-K dielectric spacer layer between metal electrodes, formed using techniques like ALD and PVD, enhances capacitance by creating a vertical sandwich structure that allows for increased surface area integration in integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional horizontal MIM capacitor structure is used, then manufacturing process is simple, but capacitance per unit area is limited
Solution Approach 1:
The patent transitions from a planar horizontal MIM capacitor structure to a vertical three-dimensional structure. The capacitor electrodes are arranged vertically with the insulating layer between them, extending in the depth direction rather than spreading horizontally. This dimensional change allows the capacitor to utilize the vertical space within the interconnection structure, significantly increasing capacitance per unit area while maintaining compatibility with standard semiconductor manufacturing processes.
2Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated, but MIM capacitor charge storage capability deteriorates
Solution Approach 1:
By transitioning to a vertical capacitor structure that extends in the depth direction of the interconnection layers, the invention increases the effective electrode surface area without increasing the horizontal footprint. This allows the capacitor to maintain or improve charge storage capability while occupying less planar area, thereby supporting higher integration density.
Solution Approach 2:
The vertical MIM capacitor structure is nested within the existing multi-layer interconnection structure of the semiconductor device. The capacitor electrodes are formed between and among the interconnection layers, utilizing the vertical space within the device cross-section. This nesting approach allows the capacitor to coexist with other device components without requiring additional horizontal area.
3Area of stationary object
If vertical MIM capacitor structure is implemented, then capacitance per unit area increases, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process for the vertical MIM capacitor is merged with the existing interconnection structure fabrication process. The same deposition, etching, and planarization techniques used for forming interconnection layers are also used to form the capacitor electrodes and insulating layers. This integration of capacitor formation into the standard interconnection process flow minimizes additional manufacturing complexity while achieving the desired vertical structure.
Solution Approach 2:
The manufacturing process is designed to be multi-functional, where the same process steps serve dual purposes: forming both the interconnection structure and the vertical MIM capacitor. For example, the same dielectric layer deposition process forms both the interconnection insulation and the capacitor insulating layer, and the same etching process defines both interconnection patterns and capacitor electrode patterns. This universality reduces the need for additional specialized process equipment and steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher capacitance in a smaller surface area, improving the performance and integration density of semiconductor devices by effectively addressing the limitations of traditional horizontal MIM capacitors.
Implementation Method 1
formed using techniques like ALD and PVD
Implementation Method 2
formed using techniques like ALD and PVD
Data Source
AI summary
A fabrication method is disclosed. The fabrication method includes: forming, on a substrate, a transistor comprising a source, drain, and gate; forming a multi-layer interconnection structure configured to provide electrical connections for the source, drain, and gate, wherein the multi-layer interconnection structure has a plurality of interconnection layers; forming a metal-insulator-metal (MiM) capacitor in the interconnection structure, the MiM capacitor comprising a first electrode, a high-K spacer with a first vertically-extending sidewall and a second vertically-extending sidewall wherein the first vertically-extending sidewall has a vertically extending interface with the first electrode, and a second electrode wherein the second vertically-extending sidewall has a vertically extending interface with the second electrode; forming a first conductive feature that connects to the first electrode; and forming a second conductive feature that connects to the second electrode.