High-k Charge Trapping Layer for 3D NAND Memory
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Solution Overview
Problem
Conventional non-volatile memory cells using silicon nitride for charge storage face limitations in trap density and data retention, especially with thicker layers which increase overall thickness and reduce capacitive coupling, leading to lower cell performance.
Innovation Solution
The use of a high-k charge storage region with multiple layers, including a high-k dielectric as the middle layer, enhances trap density and capacitive coupling, allowing for thinner layers and improved performance by incorporating high-k materials like HfO2 and ZrO2, which provide better charge storage capacity and reduced operating voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If silicon nitride is used for charge storage with thicker layers, then charge storage capacity is improved, but overall thickness increases and capacitive coupling decreases
Solution Approach 1:
The patent employs a composite charge storage region comprising multiple layers with different dielectric constants (k-values). Specifically, it uses a first charge trapping layer with k=3.9-7.9, a second charge trapping layer with k>7.9 (high-k material), and optionally a third charge trapping layer with k=3.9-7.9. This composite structure enables higher trap density and better charge storage capacity while maintaining thinner overall dimensions and improved capacitive coupling to the channel.
2Quantity of substance
If silicon nitride is used for charge storage with thicker layers, then charge storage capacity is improved, but cell performance decreases due to reduced capacitive coupling
Solution Approach 1:
The composite charge storage region with high-k material (k>7.9) in the middle layer provides enhanced trap density and improved capacitive coupling to the channel. This configuration achieves both high charge storage capacity and maintained cell performance, resolving the trade-off between storage capacity and performance.
Solution Approach 2:
The patent applies local quality by positioning the high-k material specifically in the middle charge trapping layer where it can most effectively enhance trap density and capacitive coupling. The outer layers use lower-k materials to provide appropriate band offsets for charge injection and retention, creating an optimized local structure at each interface.
3Quantity of substance
If high-k materials are used to enhance trap density, then charge storage capacity improves, but manufacturing complexity increases
Solution Approach 1:
The charge storage region is segmented into multiple discrete layers with different k-values. This segmentation allows each layer to be independently optimized for its specific function (charge trapping, capacitive coupling, band offset control) while maintaining a manageable manufacturing process through sequential deposition of distinct material layers.
Solution Approach 2:
By using composite materials with different k-values in specific positions, the patent achieves high trap density through the high-k middle layer while the outer lower-k layers provide interface quality and band alignment. This composite approach balances performance enhancement with manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves memory cell current, program and erase speed, and data retention while enabling smaller chip sizes and better vertical scaling in 3D NAND structures.
Implementation Method 1
a second charge trapping layer comprising a high-k dielectric with k>7.9
Implementation Method 2
The memory cell is programmed by injecting electrons from the memory cell channel into the charge trapping region
Implementation Method 3
The cell may be erased by injecting holes from the channel into the charge trapping region where they recombine with electrons, and thereby 'cancel' or reduce the stored charge
Data Source
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AI summary
A non-volatile storage device with memory cells having a high-k charge storage region, as well as methods of fabrication, is disclosed. The charge storage region has three or more layers of dielectric materials. At least one layer is a high-k material. The high-k layer(s) has a higher trap density as compared to S13N4. High-k dielectrics in the charge storage region enhance capacitive coupling with the memory cell channel, which can improve memory cell current, program speed, and erase speed. The charge storage region has a high-low-high conduction band offset, which may improve data retention. The charge storage region has a low-high-low valence band offset, which may improve erase.