High-Level Language Integrated Circuit Design
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Solution Overview
Problem
Conventional computer-aided design of integrated circuits requires significant time and effort to verify different models, as each model is developed using a different language, leading to inefficiencies in the verification process and potential errors.
Innovation Solution
A high-level language is introduced to generate a common database from which various models of an integrated circuit can be produced, including performance simulations, functional models, and synthesizable RTL code, optimizing for power savings and custom circuit layout, thereby reducing verification time and improving performance per watt of power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different code databases are used to generate various models (architectural model, RTL model, cycle accurate performance model), then each model can be developed with specialized language features, but verification time and complexity increase significantly
Solution Approach 1:
The patent introduces a unified high-level language that serves multiple functions: generating architectural models, RTL models, and cycle-accurate performance models from a single source. This universal language eliminates the need to verify multiple separate models in different languages, directly reducing verification time while maintaining the ability to produce specialized models for different purposes.
Solution Approach 2:
The patent merges the verification process by generating all model types (functional, performance, verification environments) from a single common database. This consolidation combines what were previously separate verification tasks into one unified process, significantly reducing the time and effort required to verify integrated circuit functionality across different abstraction levels.
2Ease of manufacture
If each model is developed using a different language, then language-specific optimizations can be applied, but the verification process becomes more complex and error-prone
Solution Approach 1:
The high-level language provides universal functionality to generate all types of models (architectural, RTL, performance) and verification environments from a single source. This eliminates the complexity of managing multiple language-specific development processes and verification workflows, while still allowing specialized optimizations through the unified language's structured approach.
Solution Approach 2:
The common database acts as an intermediary that mediates between the high-level language source code and various target models. This intermediary structure simplifies the verification process by providing a consistent interface and data structure that bridges all model types, reducing errors and complexity in the verification process.
3Reliability
If manual verification testbenches and assertions are written for each model, then thorough verification can be achieved, but significant man and machine hours are required
Solution Approach 1:
The system enables self-service verification by automatically generating verification environments and testbenches from the unified high-level language source code. The verification components are generated automatically through the common database, eliminating the need for manual verification testbench writing while maintaining thorough verification coverage, thus significantly improving verification productivity.
Solution Approach 2:
The verification environments and testbenches are prepared in advance through automatic generation from the common database before actual verification execution. This preliminary action of generating verification components automatically reduces the time required for manual verification setup while ensuring comprehensive verification coverage is maintained.
Data Source
AI summary
Systems and methods for designing and generating integrated circuits using a high-level language are described. The high-level language is used to generate performance models, functional models, synthesizable register transfer level code defining the integrated circuit, and verification environments. The high-level language may be used to generate templates for custom computation logical units for specific user-determined functionality. The high-level language and compiler permit optimizations for power savings and custom circuit layout, resulting in integrated circuits with improved performance per watt of power consumption.