High-Level Synthesis for Pipelined Stream Processor Control Logic
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Solution Overview
Problem
Existing stream processing technologies face limitations in optimizing control logic for pipelined hardware, leading to inefficient resource utilization and performance bottlenecks due to the complexity of optimizing control logic at the Register Transfer Level (RTL) stage, which restricts global optimization and increases hardware resource consumption.
Innovation Solution
The method involves using high-level synthesis to configure control logic for a pipelined parallel stream processor by partitioning data paths into discrete regions, assigning discrete control logic elements, and utilizing phase transition registers to align data across different clock phases, thereby optimizing hardware design and resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If control logic is optimized at the RTL stage, then the hardware design can be implemented, but the optimization is limited and cannot achieve global optimization due to the complexity of the stream processor design
Solution Approach 1:
The patent segments the stream processor design into distinct modules: data path modules and control logic modules. This segmentation allows independent optimization of each module while maintaining their coordinated operation. The data path is divided into functional units that can be separately analyzed and optimized, and the control logic is separated into control elements that can be independently synthesized and optimized, thereby enabling global optimization despite the overall system complexity.
2Speed
If additional hardware resources are allocated for control logic, then timing performance can be improved, but hardware resource consumption increases
Solution Approach 1:
The patent employs parameter changes by introducing clock phase parameters and timing parameters that can be adjusted to optimize the interaction between control logic and data path. By varying clock phase offsets and timing parameters, the system achieves improved timing performance without proportionally increasing hardware resources. The high-level synthesis process automatically adjusts these parameters to find optimal configurations that balance speed and resource usage.
3Productivity
If the stream processor is designed with high-level synthesis, then global optimization can be achieved, but the design complexity at higher abstraction level increases
Solution Approach 1:
The patent introduces an intermediary high-level synthesis process that acts as a mediator between the abstract design specification and the concrete hardware implementation. This intermediary layer translates high-level data path and control logic descriptions into optimized hardware configurations, enabling global optimization without requiring the designer to manage the complexity of low-level hardware details. The synthesis tool automatically handles the complexity transformation from high-level abstractions to implementable hardware.
Data Source
AI summary
A method of utilizing high level synthesis to automatically configure control logic of a hardware design for a pipelined parallel stream processor includes obtaining a scheduled graph representing a processing operation in the time domain as a function of clock cycles. The graph comprises a data path to be implemented in hardware as part of said stream processor, an input, an output, and parallel branches to enable data values to be streamed therethrough from the input to the output as a function of increasing clock cycle. The data path is partitioned to divide it into a plurality of discrete regions. Discrete control logic elements are assigned to each region using high level synthesis. The graph and assigned control logic is used to define a hardware design for the pipelined parallel stream processor.