High-Power FET Switch Biasing Without Negative Voltage Rails
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Solution Overview
Problem
Existing high power semiconductor switches require complex and area-intensive components like negative voltage generators and DC blocking capacitors, which introduce noise, increase IC die area, and consume extra power, while also experiencing higher insertion loss due to the use of n-FETs and p-FETs respectively.
Innovation Solution
A series-shunt switch design utilizing a combination of n-type and p-type FETs, where the drain and source of both types are held at similar biasing voltages in both series and shunt modes, eliminating the need for negative voltage generators and minimizing the use of blocking capacitors, thereby reducing noise, area usage, and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If negative voltage generators are used to bias FET switches, then high isolation and low insertion loss are achieved, but device complexity and IC die area increase
Solution Approach 1:
The patent extracts and eliminates the negative voltage generator from the switch circuit by redesigning the biasing architecture. Instead of using separate negative voltage sources, the invention uses only positive voltage supplies combined with DC blocking capacitors to achieve the same biasing effect, thereby removing the complex negative voltage generation hardware while maintaining high isolation performance.
Solution Approach 2:
The DC blocking capacitors in the patent serve multiple functions: they block DC voltage from reaching the FET gates, enable the use of only positive voltage supplies, and facilitate the biasing of both series and shunt FETs. This multi-functionality replaces the need for dedicated negative voltage generators, reducing device complexity while maintaining reliability.
2Reliability
If DC blocking capacitors are used to bias FET switches, then high isolation is achieved, but IC die area and power consumption increase
Solution Approach 1:
The patent changes the voltage parameters by using only positive voltage supplies instead of requiring negative voltage sources. This parameter change allows the use of smaller, more efficient DC blocking capacitors that can handle the voltage requirements with smaller capacitance values, thereby reducing the IC die area occupied by these capacitors while maintaining the high isolation performance.
3Loss of energy
If n-FETs are used for low insertion loss, then signal transmission efficiency improves, but harmonic generation increases due to parasitic diode modulation
Solution Approach 1:
The patent applies preliminary biasing actions to the FET gates through DC blocking capacitors, which pre-establish the operating point of the FETs. This preliminary action ensures that the FETs operate in an optimal region that minimizes both insertion loss and harmonic generation by controlling the bias conditions before the RF signal is applied, thereby reducing the modulation of parasitic diodes.
4Reliability
If series FET groups are used for signal path control, then isolation performance improves, but device complexity and area increase
Solution Approach 1:
The patent merges the biasing functions for series and shunt FET groups into a unified biasing architecture using only positive voltage supplies and shared DC blocking capacitors. This merging eliminates the need for separate negative voltage generators for each FET group, reducing device complexity while maintaining the high isolation performance achieved through series FET configuration.
Data Source
AI summary
A circuit and method are provided for switching in a semiconductor based high power switch. Complementary p-type based transistors are utilized along insertion loss insensitive paths allowing biasing voltages to alternate between supply and ground, allowing for negative voltage supplies and blocking capacitors to be dispensed with, while improving performance.