High Power Semiconductor Device With RESURF Structures
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Solution Overview
Problem
Traditional high power semiconductor devices face challenges with high voltage tolerance and large device area, making integration difficult and increasing manufacturing costs due to excessive device region isolation and surface field limitations.
Innovation Solution
The implementation of reduced surface field (RESURF) structures, both two-dimensional and three-dimensional, in high power semiconductor devices to enhance breakdown voltage and reduce surface field, allowing for higher voltage tolerance while minimizing device area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional isolation structures (P-type deep heavily doped regions) are used to isolate high power devices, then device isolation is achieved, but device area increases and integration becomes difficult
Solution Approach 1:
The patent extracts and removes the P-type deep heavily doped isolation regions from the device structure. By eliminating these isolation regions entirely and relying on the intrinsic isolation properties of the semiconductor layers and junctions, the device achieves adequate isolation without occupying additional area, thus resolving the contradiction between reliable isolation and compact device footprint
Solution Approach 2:
The patent merges the isolation function into the existing device structure by utilizing the P-type body regions and N-type drift region junctions to provide both device operation and isolation functions simultaneously. This integration eliminates the need for separate isolation structures, reducing overall device area while maintaining reliable electrical isolation
2Reliability
If the drift region length is increased to raise voltage tolerance in LDMOSFETs, then voltage tolerance improves, but device area increases
Solution Approach 1:
The patent applies local quality by creating a non-uniform doping profile in the drift region with varying doping concentrations at different locations. The drift region has higher doping near the drain and lower doping toward the source, which optimizes the electric field distribution to achieve high voltage tolerance without requiring excessive drift region length, thus maintaining compact device area
Solution Approach 2:
The patent transitions from a one-dimensional voltage blocking approach (relying solely on drift region length) to a two-dimensional approach by incorporating vertical P-type body regions that extend into the drift region. This creates a three-dimensional junction structure that provides voltage tolerance through both horizontal drift region design and vertical junction depth, achieving high voltage capability without proportionally increasing device area
Data Source
AI summary
Semiconductor devices for high voltage application are presented. A high power semiconductor device includes a first type doped semiconductor substrate and a second type doped epitaxial layer deposited thereon. A first type doped body region is disposed in the second type doped epitaxial layer. A heavily doped drain region is formed in the second type doped epitaxial layer and isolated from the first type doped body region with an isolation region and a channel. A second type deep heavily doped region extends from the heavily doped drain region to the semiconductor substrate. A pair of inversed type heavily doped source regions is disposed in the first type doped body region. A gate electrode is disposed overlying the channel with a dielectric layer interposed therebetween. The high power semiconductor device is isolated from the other semiconductor devices with a first type deep heavily doped region.