High-Precision Synchronization Receiver Using Marker Data and PLL
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Solution Overview
Problem
Existing wireless communication technologies face limitations in achieving high precision synchronization due to real-world influences such as component speed and accuracy, as well as traffic and noise on wireless mediums, leading to suboptimal synchronization accuracy.
Innovation Solution
A combination of network-based synchronization and phase lock loop (PLL) methods is employed, utilizing marker data and frequency changes to achieve synchronization with precision in the order of hundreds of femtoseconds, using signals like WiFi, RF, IR, and sound.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If network-based synchronization is used, then synchronization can be achieved between devices, but the accuracy is limited to milliseconds due to real-world influences
Solution Approach 1:
The patent introduces marker data as an intermediary element that carries precise timing information through the noisy wireless medium. These markers serve as reference points that allow the receiver to accurately determine timing relationships despite the presence of traffic and noise, effectively mediating between the transmission and reception processes while maintaining high precision synchronization.
Solution Approach 2:
The patent replaces traditional network-based time synchronization protocols (which rely on packet exchange and timestamp comparison) with a physics-based approach using phase-locked loops and frequency domain analysis. This substitution allows the system to achieve femtosecond-level precision by analyzing the phase and frequency characteristics of received signals rather than relying on software-based timestamp processing.
2Measurement precision
If traditional synchronization methods are used, then device coordination is possible, but precision is limited to milliseconds
Solution Approach 1:
The patent fundamentally changes the time measurement parameter from millisecond-level network timestamps to femtosecond-level phase and frequency measurements. By operating in the frequency domain and using phase-locked loops, the system extracts timing information with much higher precision, transforming the synchronization approach from coarse-grained packet-based timing to fine-grained signal-based timing.
Solution Approach 2:
The patent segments the synchronization process into distinct functional components: marker data generation, frequency domain signal processing, phase detection, and clock adjustment. This segmentation allows each component to be optimized independently and facilitates the integration of complex processing techniques while maintaining overall system manageability.
3Measurement precision
If higher precision synchronization is achieved through additional processing, then accuracy improves to hundreds of femtoseconds, but system complexity increases
Solution Approach 1:
The patent employs periodic marker signals that are transmitted at regular intervals and contain known frequency characteristics. The phase-locked loop continuously tracks these periodic signals, and the Fast Fourier Transform analyzes periodic frequency components to determine precise timing. This periodic structure simplifies the processing by providing predictable, repeating patterns that are easier to analyze than arbitrary signals.
Solution Approach 2:
The patent implements feedback mechanisms where the received marker signals are used to continuously adjust the local clock frequency and phase. The phase-locked loop provides automatic feedback control by comparing the received signal phase with the local oscillator phase and adjusting accordingly. This feedback approach enables the system to achieve and maintain high precision synchronization without requiring complex open-loop calculations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances synchronization accuracy from milliseconds to hundreds of femtoseconds by leveraging marker data and PLL techniques, improving synchronization precision across electronic devices in a shared medium.
Implementation Method 1
The PLL circuit performs PLL synchronization based on a frequency change, amplitude change, or a presence change of the second signal.
Data Source
AI summary
Some embodiments include an apparatus, method, and computer program product for high precision device synchronization of electronic devices in a shared medium. Some embodiments include a first electronic device that utilizes a combination of synchronization techniques to synchronize with a second electronic device. The first electronic device receives a first signal from the second electronic device that includes network-based synchronization data and marker data, and performs network-based synchronization with the second electronic device at a first synchronization accuracy. The first electronic device receives a second signal, and uses the marker data and phase lock synchronization to detect a frequency change of the second signal received, as well as to determine a corresponding time marker. The first electronic device updates a clock of the first electronic device based at least on the corresponding time marker, the network-based synchronization data, and the marker data.