High-Rate NAND Arbitration for Host-Bandwidth-Limited SSDs
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Solution Overview
Problem
NAND flash memory systems experience performance degradation due to back pressure when the host device's bandwidth cannot keep up with the NAND's throughput, leading to inefficient utilization of the NAND's full potential.
Innovation Solution
Implement an improved NAND arbitration scheme where a device controller interleaves different sets of NANDs based on the host speed to NAND speed ratio, selecting and programming NANDs in an alternating manner to ensure continuous data transfer without pausing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If NAND flash memory operates at high throughput, then data transfer speed is improved, but back pressure accumulates when host device bandwidth is insufficient, causing performance degradation
Solution Approach 1:
The patent segments the NAND flash memory into multiple independent channels or queues, allowing the controller to distribute data transfer across multiple paths. This segmentation enables finer-grained arbitration and prevents back pressure from blocking the entire NAND interface, thereby maintaining high utilization efficiency even when host bandwidth is limited.
Solution Approach 2:
The patent implements dynamic arbitration that adapts to changing host device bandwidth conditions. The controller continuously monitors host availability and dynamically adjusts the number of NANDs actively receiving data, switching between aggressive parallelism when host bandwidth is充足 and conservative sequencing when host bandwidth is limited, thus optimizing productivity across varying operating conditions.
2Productivity
If multiple NANDs are accessed simultaneously over a shared bus, then throughput is improved, but signal integrity problems increase
Solution Approach 1:
The patent divides the shared bus access into time-multiplexed segments, where different NAND devices are accessed in alternating time slots rather than simultaneously. This segmentation reduces the number of active devices on the bus at any given moment, thereby maintaining signal integrity while still achieving high aggregate throughput through parallel time-multiplexed operations.
Solution Approach 2:
The patent employs periodic arbitration schemes where NAND devices are selected in regular alternating patterns (e.g., round-robin or interleaved patterns). This periodic action ensures that no single NAND monopolizes the bus for extended periods, allowing the bus to settle between accesses and maintaining signal integrity while achieving sustained high throughput through systematic parallel access.
3Productivity
If data transfer is paused in the middle of a page due to insufficient host data, then back pressure is relieved, but performance degradation occurs
Solution Approach 1:
The patent segments data transfer into smaller units that can be independently managed and paused without affecting the entire page transfer. By dividing the transfer into manageable chunks distributed across multiple NAND devices, the system can pause individual transfers to relieve back pressure while maintaining overall high utilization, avoiding the performance penalty of pausing entire page transfers.
Solution Approach 2:
The patent implements continuous arbitration that ensures data transfer to NAND devices proceeds without unnecessary pauses. The controller maintains a pipeline of data ready for transfer and proactively manages host-NAND data flow to prevent back pressure accumulation, thereby eliminating idle pause time and maintaining continuous useful action even when host bandwidth is limited.
Data Source
AI summary
When the overall NAND bandwidth exceeds the bandwidth of a host device, back pressure builds and the full potential of the NAND is not utilized. This back pressure may be relieved by NAND arbitration, where a device controller selects and interleaves different sets of NANDs over the course of subsequent states. The number of NANDs that participate in this arbitration depends on the host speed to NAND speed ratio. At each state, different sets of NAND are selected by exchanging NANDs that were used in a previous state with NANDS that were not used in a previous state in an interleaving manner. At each state, a pre-determined amount of data will be sent to the selected set of NAND. Once the device determines that all the NANDs participating in the arbitration are ready to be programmed, the device will program the NANDs.