High-Rate RLL Encoding With Interleaved Mother Code Structure
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Solution Overview
Problem
Current RLL codes, particularly those used in data storage, face challenges in designing higher-rate codes that satisfy constraints like G, I, and M constraints while maintaining error-rate performance and compact representation, especially for next-generation standards like LTO 5 which requires rate-32/33 or rate-48/49 codes, without increasing complexity or gate count excessively.
Innovation Solution
An algorithmic approach is developed to design higher-rate PRML(G, I, M) codes by generating a rate-16/17 mother code that enforces specific transition densities, allowing for the construction of higher-rate codes such as rate-32/33 or rate-48/49 codes by interleaving uncoded bytes with the mother code's output, ensuring constraints are met and error propagation is managed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If higher-rate RLL codes (rate-32/33 or rate-48/49) are designed to meet next-generation storage standards, then data storage efficiency is improved, but code complexity and gate count increase excessively
Solution Approach 1:
The patent segments the higher-rate RLL code design into multiple components: a base rate-16/17 code structure, uncoded byte segments, and interleaving patterns. By dividing the code into these manageable segments that can be independently designed and combined, the overall complexity is reduced while achieving the required rate-32/33 or rate-48/49 performance
Solution Approach 2:
The patent employs a nested structure where rate-16/17 coded bytes are interleaved with uncoded bytes to form higher-rate codes. The base code structure is nested within a larger framework that includes both coded and uncoded segments, allowing systematic construction of complex high-rate codes from simpler building blocks
2Manufacturing precision
If higher-rate RLL codes are designed with extensive pattern prohibitions to satisfy constraints, then constraint satisfaction is improved, but device complexity increases
Solution Approach 1:
Instead of prohibiting all possible unwanted patterns, the patent applies partial action by selectively prohibiting only the most critical patterns that violate G, I, and M constraints. This targeted approach satisfies the necessary constraints while avoiding the complexity of extensive pattern prohibitions
Solution Approach 2:
The patent changes the approach from pattern-based prohibitions to parameter-based constraint satisfaction. By focusing on satisfying G, I, and M constraints through controlled parameter selection in the base code and interleaving scheme, the system achieves constraint satisfaction with reduced complexity compared to exhaustive pattern prohibition
3Reliability
If rate-16/17 mother code with transition density enforcement is used to generate higher-rate codes, then error propagation is reduced, but encoding complexity increases
Solution Approach 1:
The patent applies preliminary action by enforcing transition density constraints during the base rate-16/17 code generation stage. By pre-establishing these constraints in the mother code structure before interleaving with uncoded bytes, the system proactively controls error propagation characteristics, reducing the need for complex error correction mechanisms later
Data Source
AI summary
An unencoded m-bit data input sequence is divided into a block of n bits and a block of m−n bits. The block of n bits is divided into a first set of n+1 encoded bits, wherein at least one of P1 subblocks of the first set satisfies a G, M and I constraints. The first set of n+1 encoded bits is mapped into a second set of n+1 encoded bits wherein at least one of P2 subblocks of the second set gives rise to at least Q1 transitions after 1/(1+D2) precoding. A second set of n+1 encoded bits is divided into P3 encoded subblocks and the P3 encoded subblocks are interleaved among (m−n)/s unencoded symbols so as to form a (m+1)-bit output sequence codeword which is then stored on a data storage medium.