High Ratio Multiplexer Memory SEU Tolerance
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Solution Overview
Problem
Conventional memory devices with 4:1 multiplexers are vulnerable to single event upsets (SEU) at advanced technology nodes due to close spacing of bit cells, leading to increased corruption of memory cells from particle strikes, making software corrections less reliable.
Innovation Solution
The use of high ratio multiplexers with an 8:1 or higher input to output ratio, such as 8:1 or 16:1 column MUXES, doubles the distance between bit cells connected to adjacent MUXES, reducing the likelihood of corruption from high energy particle strikes, while maintaining SEU tolerance without significant size increases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If bit cells are closely spaced to conserve chip area, then chip area is reduced, but vulnerability to single event upset increases
Solution Approach 1:
The patent divides the memory array into multiple segments (e.g., 8 segments) along the bit line direction, with each segment served by a separate sense amplifier. This segmentation increases the distance between adjacent bit cells that can be affected by a single particle strike, reducing SEU propagation while maintaining compact chip area through efficient spatial organization of the segmented structures.
2Device complexity
If conventional 4:1 multiplexers are used, then device complexity is low, but SEU tolerance is insufficient
Solution Approach 1:
The patent introduces a new dimension to the multiplexer design by implementing an 8:1 multiplexer structure that selects from 8 different bit line segments instead of the conventional 4:1 structure. This dimensional expansion in the selection capability increases the spacing between correlated bit cells, providing enhanced SEU tolerance while maintaining manageable device complexity through systematic design.
3Reliability
If high ratio MUXES with 8:1 or higher are used, then SEU resistance is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple bit line segments (8 segments) into a single selected bit line through the 8:1 multiplexer structure, allowing compact integration of what would otherwise require more dispersed routing. This merging approach achieves enhanced SEU resistance by increasing effective spacing while controlling device complexity through consolidated signal paths and shared control logic.
Data Source
AI summary
A memory device is disclosed herein that leverages high ratio column MUXES to improve SEU resistance. The memory device may be utilized in an integrated circuit die and chip packages having the same. In one example, as semiconductor memory device is provided that includes first and second arrays of semiconductor memory cells, a plurality of sense amplifiers configured to read data states from the first and second arrays of memory cells, and a first plurality of high ratio MUXES connecting the first and second arrays of memory cells to the plurality of sense amplifiers.