High Resistance Layer for III-V MOS Transistors
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Solution Overview
Problem
Metal-oxide-semiconductor (MOS) transistors face issues with current leakage due to shunt paths that bypass the channel region, leading to high resistance and potential short circuits, particularly when III-V materials are deposited on group IV substrates, resulting in disordered interfaces with stacking faults and dislocations.
Innovation Solution
A high resistance layer with a III-V wide bandgap material is introduced between the III-V channel layer and the group IV substrate, which can be converted to an insulator to electrically isolate the channel layer, minimizing current flow through paths other than the direct channel path, thereby reducing leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If III-V materials are deposited on group IV substrates, then the transistor channel layer can be formed, but shunt paths cause current leakage and high resistance
Solution Approach 1:
An intermediate layer is introduced between the III-V channel layer and the group IV substrate. This intermediate layer serves as a mediator that prevents direct interaction between the channel layer and substrate, thereby eliminating shunt paths and current leakage while maintaining the electrical isolation needed for proper transistor operation.
Solution Approach 2:
The interface region is segmented into multiple distinct layers including the intermediate layer, buffer layer, and channel layer. This segmentation separates the functional regions and prevents the formation of continuous shunt paths through the interface, addressing the current leakage problem while preserving channel integrity.
2Object-affected harmful factors
If a high resistance layer is introduced between the channel layer and substrate, then current leakage is reduced, but device structure becomes more complex
Solution Approach 1:
The intermediate layer performs multiple functions simultaneously: it provides electrical isolation to prevent current leakage, serves as a buffer to accommodate lattice mismatch between III-V and group IV materials, and facilitates epitaxial growth of the channel layer. This multi-functionality reduces the need for additional separate layers, thereby limiting the increase in structural complexity.
3Stability of the object's composition
If the interface between III-V layer and substrate is disordered with stacking faults and dislocations, then material diffusion occurs, but shunt paths are created causing leakage
Solution Approach 1:
The intermediate layer acts as a mediator that decouples the III-V channel layer from the group IV substrate interface. By placing this intermediate layer between the channel and substrate, the disordered interface with stacking faults and dislocations is isolated from the channel region, preventing shunt path formation while the intermediate layer itself maintains compositional stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively increases the resistance to current flow through unintended paths, enhancing the performance of MOS transistors by reducing leakage and improving the quality of III-V channel films, while being compatible with complementary MOS integration and minimizing toxicity in the manufacturing process.
Implementation Method 1
a high resistance layer sandwiched between the channel layer and the substrate, wherein the high resistance layer has a bandgap greater than 1.4 electron volts (eV) and that is greater than the bandgap of the channel layer
Implementation Method 2
the wide bandgap layer may be partially or completely converted to an insulator (or at a minimum, to a higher bandgap semiconductor) through oxidation or nitridation, for example
Implementation Method 3
the wide bandgap layer may be partially or completely converted to an insulator (or at a minimum, to a higher bandgap semiconductor) through oxidation or nitridation, for example
Data Source
Figure 1a~1b
Figure 2a~2c
Figure 3a~3c
AI summary
Techniques are disclosed for using a high resistance layer between a III-V channel layer and a group IV substrate for semiconducting devices, such as metal-oxide-semiconductor (MOS) transistors. The high resistance layer can be used to minimize (or eliminate) current flow from source to drain that follows a path other than directly through the channel. In some cases, the high resistance layer may be a III-V wide bandgap layer. In some such cases, the wide bandgap layer may have a bandgap greater than 1.4 electron volts (eV), and may even have a bandgap greater than 2.0 eV. In other cases, the wide bandgap layer may be partially or completely converted to an insulator through oxidation or nitridation, for example. The resulting structures may be used with planar, finned, or nanowire/nanoribbon transistor architectures to help prevent substrate leakage problems.